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-rw-r--r--src/vhdl/simulate/simulation.adb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/vhdl/simulate/simulation.adb b/src/vhdl/simulate/simulation.adb
index 0b01a4c88..52dc894d2 100644
--- a/src/vhdl/simulate/simulation.adb
+++ b/src/vhdl/simulate/simulation.adb
@@ -659,7 +659,7 @@ package body Simulation is
Arr := Create_Array_Value (Len, 1);
Arr.Bounds.D (1) := Create_Bounds_From_Length
(Instance.Block,
- Get_First_Element (Get_Index_Subtype_List (Arr_Type)),
+ Get_Nth_Element (Get_Index_Subtype_List (Arr_Type), 0),
Len);
-- First ports