diff options
Diffstat (limited to 'src/vhdl/simulate')
| -rw-r--r-- | src/vhdl/simulate/simul-annotations.adb | 3 | ||||
| -rw-r--r-- | src/vhdl/simulate/simul-elaboration.adb | 3 |
2 files changed, 4 insertions, 2 deletions
diff --git a/src/vhdl/simulate/simul-annotations.adb b/src/vhdl/simulate/simul-annotations.adb index 8fb4c4fdc..f807f12b7 100644 --- a/src/vhdl/simulate/simul-annotations.adb +++ b/src/vhdl/simulate/simul-annotations.adb @@ -1021,7 +1021,8 @@ package body Simul.Annotations is null; when Iir_Kind_Concurrent_Simple_Signal_Assignment - | Iir_Kind_Concurrent_Selected_Signal_Assignment => + | Iir_Kind_Concurrent_Selected_Signal_Assignment + | Iir_Kind_Concurrent_Conditional_Signal_Assignment => -- In case concurrent signal assignemnts were not -- canonicalized (for synthesis). null; diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb index f21c623eb..1638aa721 100644 --- a/src/vhdl/simulate/simul-elaboration.adb +++ b/src/vhdl/simulate/simul-elaboration.adb @@ -1903,7 +1903,8 @@ package body Simul.Elaboration is Elaborate_Psl_Directive (Instance, Stmt); when Iir_Kind_Concurrent_Simple_Signal_Assignment - | Iir_Kind_Concurrent_Selected_Signal_Assignment => + | Iir_Kind_Concurrent_Selected_Signal_Assignment + | Iir_Kind_Concurrent_Conditional_Signal_Assignment => -- In case concurrent signal assignemnts were not -- canonicalized. null; |