diff options
Diffstat (limited to 'src/vhdl/simulate')
| -rw-r--r-- | src/vhdl/simulate/simul-execution.adb | 1 | ||||
| -rw-r--r-- | src/vhdl/simulate/simul-simulation-main.adb | 2 |
2 files changed, 0 insertions, 3 deletions
diff --git a/src/vhdl/simulate/simul-execution.adb b/src/vhdl/simulate/simul-execution.adb index b96e1f173..f034bb9b6 100644 --- a/src/vhdl/simulate/simul-execution.adb +++ b/src/vhdl/simulate/simul-execution.adb @@ -584,7 +584,6 @@ package body Simul.Execution is procedure Assert_Std_Ulogic_Dc (Loc : Iir) is - use Grt.Std_Logic_1164; begin Execute_Failed_Assertion ("assertion", diff --git a/src/vhdl/simulate/simul-simulation-main.adb b/src/vhdl/simulate/simul-simulation-main.adb index 3c6903953..7d6f0e7c7 100644 --- a/src/vhdl/simulate/simul-simulation-main.adb +++ b/src/vhdl/simulate/simul-simulation-main.adb @@ -34,7 +34,6 @@ with Grt.Main; with Simul.Debugger; use Simul.Debugger; with Simul.Debugger.AMS; with Grt.Errors; -with Grt.Rtis; with Grt.Processes; with Grt.Signals; with Areapools; use Areapools; @@ -1033,7 +1032,6 @@ package body Simul.Simulation.Main is Sig : Iir_Value_Literal_Acc; Val : Iir_Value_Literal_Acc) is - use Grt.Rtis; use Grt.Signals; procedure Create_Signal (Val : Iir_Value_Literal_Acc; |