diff options
Diffstat (limited to 'src/vhdl/vhdl-evaluation.adb')
| -rw-r--r-- | src/vhdl/vhdl-evaluation.adb | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/src/vhdl/vhdl-evaluation.adb b/src/vhdl/vhdl-evaluation.adb index 8cb22f5c9..0cf803f97 100644 --- a/src/vhdl/vhdl-evaluation.adb +++ b/src/vhdl/vhdl-evaluation.adb @@ -858,8 +858,8 @@ package body Vhdl.Evaluation is for I in Flist_First .. Last loop -- Elements are static. Val := Get_Nth_Element (Els, I); - Write_Discrete (Res.Mem + Size_Type (I) * Typ.Vec_El.Sz, - Typ.Vec_El, Eval_Pos (Val)); + Write_Discrete (Res.Mem + Size_Type (I) * Typ.Arr_El.Sz, + Typ.Arr_El, Eval_Pos (Val)); end loop; end; when Iir_Kind_String_Literal8 => @@ -880,7 +880,7 @@ package body Vhdl.Evaluation is Lit := Get_Nth_Element (Literal_List, Natural (Str_Table.Element_String8 (Id, I))); - Write_Discrete (Res.Mem + Size_Type (I - 1), Typ.Vec_El, + Write_Discrete (Res.Mem + Size_Type (I - 1), Typ.Arr_El, Int64 (Get_Enum_Pos (Lit))); end loop; end; @@ -952,7 +952,7 @@ package body Vhdl.Evaluation is Idx_Type : Iir; begin Idx_Type := Create_Range_Subtype_From_Type (Base_Idx, Loc); - Rng := Convert_Bound_To_Node (Typ.Vbound, Base_Idx, Orig); + Rng := Convert_Bound_To_Node (Typ.Abound, Base_Idx, Orig); Set_Range_Constraint (Idx_Type, Rng); Res := Create_Array_Subtype (Btype, Loc); @@ -976,7 +976,7 @@ package body Vhdl.Evaluation is Literal_List : constant Iir_Flist := Get_Enumeration_Literal_List (Element_Type); - Len : constant Nat32 := Nat32 (Mt.Typ.Vbound.Len); + Len : constant Nat32 := Nat32 (Mt.Typ.Abound.Len); List : Iir_Flist; El : Int64; @@ -986,7 +986,7 @@ package body Vhdl.Evaluation is for I in 1 .. Len loop El := Read_Discrete (Mt.Mem + Size_Type (I - 1), - Mt.Typ.Vec_El); + Mt.Typ.Arr_El); Lit := Get_Nth_Element (Literal_List, Natural (El)); Set_Nth_Element (List, Natural (I - 1), Lit); end loop; @@ -2585,8 +2585,7 @@ package body Vhdl.Evaluation is | Iir_Predefined_Bit_Array_Match_Inequality | Iir_Predefined_Std_Ulogic_Array_Match_Equality | Iir_Predefined_Std_Ulogic_Array_Match_Inequality => - -- TODO - raise Internal_Error; + return Eval_Ieee_Operator (Orig, Imp, Left, Right); when Iir_Predefined_Enum_To_String | Iir_Predefined_Integer_To_String @@ -4061,23 +4060,24 @@ package body Vhdl.Evaluation is end if; end Eval_Expr_Check_If_Static; - function Eval_Int_In_Range (Val : Int64; Bound : Iir) return Boolean is + function Eval_Int_In_Range (Val : Int64; Bound : Iir) return Boolean + is + L, R : Iir; begin case Get_Kind (Bound) is when Iir_Kind_Range_Expression => + L := Get_Left_Limit (Bound); + R := Get_Right_Limit (Bound); + if Get_Kind (L) = Iir_Kind_Overflow_Literal + or else Get_Kind (R) = Iir_Kind_Overflow_Literal + then + return True; + end if; case Get_Direction (Bound) is when Dir_To => - if Val < Eval_Pos (Get_Left_Limit (Bound)) - or else Val > Eval_Pos (Get_Right_Limit (Bound)) - then - return False; - end if; + return Val >= Eval_Pos (L) and then Val <= Eval_Pos (R); when Dir_Downto => - if Val > Eval_Pos (Get_Left_Limit (Bound)) - or else Val < Eval_Pos (Get_Right_Limit (Bound)) - then - return False; - end if; + return Val <= Eval_Pos (L) and then Val >= Eval_Pos (R); end case; when others => Error_Kind ("eval_int_in_range", Bound); |