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-rw-r--r--src/vhdl/vhdl-sem_specs.adb10
1 files changed, 7 insertions, 3 deletions
diff --git a/src/vhdl/vhdl-sem_specs.adb b/src/vhdl/vhdl-sem_specs.adb
index 38a808440..e75c786fb 100644
--- a/src/vhdl/vhdl-sem_specs.adb
+++ b/src/vhdl/vhdl-sem_specs.adb
@@ -1268,7 +1268,11 @@ package body Vhdl.Sem_Specs is
if Is_Error (Entity_Name) then
return Null_Iir;
end if;
- Entity_Name := Sem_Denoting_Name (Get_Entity_Name (Aspect));
+ if Get_Kind (Entity_Name) not in Iir_Kinds_Denoting_Name then
+ Error_Msg_Sem (+Entity_Name, "name of an entity expected");
+ return Null_Iir;
+ end if;
+ Entity_Name := Sem_Denoting_Name (Entity_Name);
Set_Entity_Name (Aspect, Entity_Name);
Entity := Get_Named_Entity (Entity_Name);
if Entity = Error_Mark then
@@ -1350,7 +1354,7 @@ package body Vhdl.Sem_Specs is
end Sem_Entity_Aspect;
procedure Sem_Check_Missing_Generic_Association
- (Inter_Chain : Iir; Assoc1 : Iir; Assoc2 : Iir; Loc : Iir)
+ (Inter_Chain : Iir; Assoc1 : Iir; Assoc2 : Iir; Loc : Iir)
is
Inter : Iir;
Inter_Iter : Iir;
@@ -1389,7 +1393,7 @@ package body Vhdl.Sem_Specs is
if Get_Open_Flag (Inter) then
Set_Open_Flag (Inter, False);
Err := Sem_Check_Missing_Association
- (Inter, Missing_Generic, True, Loc);
+ (Inter, Missing_Generic, True, False, Loc);
end if;
Inter := Get_Chain (Inter);
end loop;