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-rw-r--r--src/vhdl/vhdl-ieee-std_logic_arith.adb10
-rw-r--r--src/vhdl/vhdl-nodes.ads3
2 files changed, 13 insertions, 0 deletions
diff --git a/src/vhdl/vhdl-ieee-std_logic_arith.adb b/src/vhdl/vhdl-ieee-std_logic_arith.adb
index 4c2b517ec..c1d7caccf 100644
--- a/src/vhdl/vhdl-ieee-std_logic_arith.adb
+++ b/src/vhdl/vhdl-ieee-std_logic_arith.adb
@@ -397,6 +397,16 @@ package body Vhdl.Ieee.Std_Logic_Arith is
Def := Handle_Cmp (Eq_Patterns);
when Name_Op_Inequality =>
Def := Handle_Cmp (Ne_Patterns);
+ when Name_Ext =>
+ if Arg1_Kind /= Type_Slv or Arg2_Kind /= Type_Int then
+ raise Error;
+ end if;
+ Def := Iir_Predefined_Ieee_Std_Logic_Arith_Ext;
+ when Name_Sxt =>
+ if Arg1_Kind /= Type_Slv or Arg2_Kind /= Type_Int then
+ raise Error;
+ end if;
+ Def := Iir_Predefined_Ieee_Std_Logic_Arith_Sxt;
when others =>
null;
end case;
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index c6f7d0891..393780a3f 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -5782,6 +5782,9 @@ package Vhdl.Nodes is
Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Sgn,
Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Log,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Ext,
+ Iir_Predefined_Ieee_Std_Logic_Arith_Sxt,
+
Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Uns_Uns_Uns,
Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Sgn_Sgn,
Iir_Predefined_Ieee_Std_Logic_Arith_Mul_Sgn_Uns_Sgn,