diff options
Diffstat (limited to 'src/vhdl')
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_1164.adb | 14 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 8 |
2 files changed, 16 insertions, 6 deletions
diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb index 58fe96229..bb4b12bce 100644 --- a/src/vhdl/vhdl-ieee-std_logic_1164.adb +++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb @@ -375,11 +375,17 @@ package body Vhdl.Ieee.Std_Logic_1164 is when Name_Not => Predefined := Iir_Predefined_Ieee_1164_Vector_Not; when Name_And => - Predefined := - Iir_Predefined_Ieee_1164_Vector_And_Reduce; + Predefined := Iir_Predefined_Ieee_1164_And_Suv; + when Name_Nand => + Predefined := Iir_Predefined_Ieee_1164_Nand_Suv; when Name_Or => - Predefined := - Iir_Predefined_Ieee_1164_Vector_Or_Reduce; + Predefined := Iir_Predefined_Ieee_1164_Or_Suv; + when Name_Nor => + Predefined := Iir_Predefined_Ieee_1164_Nor_Suv; + when Name_Xor => + Predefined := Iir_Predefined_Ieee_1164_Xor_Suv; + when Name_Xnor => + Predefined := Iir_Predefined_Ieee_1164_Xnor_Suv; when Name_Is_X => Predefined := Iir_Predefined_Ieee_1164_Scalar_Is_X; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 2460e7bfc..8f3c003fa 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5471,8 +5471,12 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_1164_Falling_Edge, -- VHDL-2008 unary logic operators - Iir_Predefined_Ieee_1164_Vector_And_Reduce, - Iir_Predefined_Ieee_1164_Vector_Or_Reduce, + Iir_Predefined_Ieee_1164_And_Suv, + Iir_Predefined_Ieee_1164_Nand_Suv, + Iir_Predefined_Ieee_1164_Or_Suv, + Iir_Predefined_Ieee_1164_Nor_Suv, + Iir_Predefined_Ieee_1164_Xor_Suv, + Iir_Predefined_Ieee_1164_Xnor_Suv, Iir_Predefined_Ieee_1164_Vector_Sll, Iir_Predefined_Ieee_1164_Vector_Srl, |