diff options
Diffstat (limited to 'src/vhdl')
42 files changed, 1828 insertions, 628 deletions
diff --git a/src/vhdl/translate/trans-chap14.adb b/src/vhdl/translate/trans-chap14.adb index 31c000bd3..c66961954 100644 --- a/src/vhdl/translate/trans-chap14.adb +++ b/src/vhdl/translate/trans-chap14.adb @@ -31,22 +31,57 @@ with Trans.Foreach_Non_Composite; package body Trans.Chap14 is use Trans.Helpers; + function Translate_Name_Bounds (Name : Iir) return Mnode + is + Res : Mnode; + begin + case Get_Kind (Name) is + when Iir_Kinds_Denoting_Name => + return Translate_Name_Bounds (Get_Named_Entity (Name)); + when Iir_Kind_Type_Declaration + | Iir_Kind_Subtype_Declaration => + Res := T2M (Get_Type (Name), Mode_Value); + Res := Chap3.Get_Composite_Bounds (Res); + return Res; + when Iir_Kinds_Object_Declaration + | Iir_Kind_Stable_Attribute + | Iir_Kind_Quiet_Attribute + | Iir_Kind_Delayed_Attribute + | Iir_Kind_Transaction_Attribute + | Iir_Kind_Image_Attribute + | Iir_Kind_Indexed_Name + | Iir_Kind_Selected_Element + | Iir_Kind_Slice_Name + | Iir_Kind_Dereference + | Iir_Kind_Implicit_Dereference + | Iir_Kind_Function_Call => + -- Prefix is an object. + Res := Chap6.Translate_Name (Name, Mode_Value); + Res := Chap3.Get_Composite_Bounds (Res); + return Res; + when Iir_Kind_Element_Attribute => + declare + Pfx : constant Iir := Get_Prefix (Name); + Pfx_Type : constant Iir := Get_Type (Pfx); + begin + Res := Translate_Name_Bounds (Pfx); + Res := Chap3.Array_Bounds_To_Element_Bounds (Res, Pfx_Type); + return Res; + end; + when others => + Error_Kind ("translate_name_bounds", Name); + end case; + end Translate_Name_Bounds; + function Translate_Array_Attribute_To_Range (Expr : Iir) return Mnode is - Prefix : constant Iir := Get_Prefix (Expr); - Type_Name : constant Iir := Is_Type_Name (Prefix); - Arr : Mnode; - Dim : Natural; + Prefix : constant Iir := Get_Prefix (Expr); + Bnd : Mnode; + Dim : Natural; begin - if Type_Name /= Null_Iir then - -- Prefix denotes a type name - Arr := T2M (Type_Name, Mode_Value); - else - -- Prefix is an object. - Arr := Chap6.Translate_Name (Prefix, Mode_Value); - end if; + Bnd := Translate_Name_Bounds (Prefix); Dim := Eval_Attribute_Parameter_Or_1 (Expr); - return Chap3.Get_Array_Range (Arr, Get_Type (Prefix), Dim); + return Chap3.Bounds_To_Range (Bnd, Get_Type (Prefix), Dim); end Translate_Array_Attribute_To_Range; function Translate_Range_Array_Attribute (Expr : Iir) diff --git a/src/vhdl/translate/trans-chap4.adb b/src/vhdl/translate/trans-chap4.adb index d9feeb16d..f1db4d40b 100644 --- a/src/vhdl/translate/trans-chap4.adb +++ b/src/vhdl/translate/trans-chap4.adb @@ -3123,6 +3123,7 @@ package body Trans.Chap4 is Entity : Iir) is pragma Unreferenced (Num); + use Trans.Chap5; Formal : constant Iir := Get_Association_Formal (Assoc, Inter); Actual : constant Iir := Get_Actual (Assoc); Block_Info : constant Block_Info_Acc := Get_Info (Base_Block); @@ -3131,6 +3132,7 @@ package body Trans.Chap4 is Entity_Info : Ortho_Info_Acc; Targ : Mnode; Val : Mnode; + Act_Env : Map_Env; begin -- Declare the subprogram. Assoc_Info := Add_Info (Assoc, Kind_Inertial_Assoc); @@ -3153,6 +3155,7 @@ package body Trans.Chap4 is Open_Temp; -- Access for formals. + Act_Env.Scope_Ptr := null; if Entity /= Null_Iir then Entity_Info := Get_Info (Entity); declare @@ -3177,9 +3180,13 @@ package body Trans.Chap4 is Inst_Info.Block_Link_Field), Rtis.Ghdl_Component_Link_Instance)), Entity_Info.Block_Decls_Ptr_Type)); + -- Save previous scope for recursive instantiation. + Save_Map_Env (Act_Env, Entity_Info.Block_Scope'Access); + if not Is_Null (Entity_Info.Block_Scope) then + Clear_Scope (Entity_Info.Block_Scope); + end if; Set_Scope_Via_Param_Ptr (Entity_Info.Block_Scope, V); end if; - end; end if; @@ -3187,6 +3194,11 @@ package body Trans.Chap4 is -- 1. Translate target (translate_name) Targ := Chap6.Translate_Name (Formal, Mode_Signal); + if Act_Env.Scope_Ptr /= null then + -- Switch to the actual environment (if any). + Set_Map_Env (Act_Env); + end if; + -- 2. Translate expression Val := Chap7.Translate_Expression (Actual, Get_Type (Formal)); @@ -3201,9 +3213,10 @@ package body Trans.Chap4 is if Entity /= Null_Iir then if Entity_Info.Kind = Kind_Component then + pragma Assert (Act_Env.Scope_Ptr = null); Clear_Scope (Entity_Info.Comp_Scope); else - Clear_Scope (Entity_Info.Block_Scope); + Restore_Map_Env (Act_Env); end if; end if; diff --git a/src/vhdl/translate/trans-chap5.ads b/src/vhdl/translate/trans-chap5.ads index ab54e67da..88627da56 100644 --- a/src/vhdl/translate/trans-chap5.ads +++ b/src/vhdl/translate/trans-chap5.ads @@ -42,6 +42,7 @@ package Trans.Chap5 is -- Save and restore the map environment defined by ENV. procedure Save_Map_Env (Env : out Map_Env; Scope_Ptr : Var_Scope_Acc); procedure Set_Map_Env (Env : Map_Env); + procedure Restore_Map_Env (Env : Map_Env); procedure Elab_Generic_Map_Aspect (Header : Iir; Map : Iir; Formal_Env : Map_Env); diff --git a/src/vhdl/translate/trans-chap7.adb b/src/vhdl/translate/trans-chap7.adb index bd80b1050..17eb783ea 100644 --- a/src/vhdl/translate/trans-chap7.adb +++ b/src/vhdl/translate/trans-chap7.adb @@ -4408,15 +4408,19 @@ package body Trans.Chap7 is function Translate_Overflow_Literal (Expr : Iir) return O_Enode is Expr_Type : constant Iir := Get_Type (Expr); - Tinfo : constant Type_Info_Acc := Get_Info (Expr_Type); - Otype : constant O_Tnode := Tinfo.Ortho_Type (Mode_Value); + Tinfo : Type_Info_Acc; + Otype : O_Tnode; L : O_Dnode; begin + Chap3.Translate_Anonymous_Subtype_Definition (Expr_Type, False); + -- Generate the error message Chap6.Gen_Bound_Error (Expr); -- Create a dummy value, for type checking. But never -- executed. + Tinfo := Get_Info (Expr_Type); + Otype := Tinfo.Ortho_Type (Mode_Value); L := Create_Temp (Otype); if Tinfo.Type_Mode in Type_Mode_Fat then -- For fat pointers or arrays. diff --git a/src/vhdl/translate/trans-chap8.adb b/src/vhdl/translate/trans-chap8.adb index 2b24e3737..05cac2c56 100644 --- a/src/vhdl/translate/trans-chap8.adb +++ b/src/vhdl/translate/trans-chap8.adb @@ -3307,7 +3307,9 @@ package body Trans.Chap8 is -- Set the PARAMS field. Assign_Params_Field (M2E (Mval), Mode_Value); end if; - elsif Formal_Info.Interface_Field (Mode_Value) /= O_Fnode_Null then + elsif Formal_Info.Interface_Decl (Mode_Value) = O_Dnode_Null + and then Formal_Info.Interface_Field (Mode_Value) /= O_Fnode_Null + then Assign_Params_Field (Val, Mode_Value); if Sig /= O_Enode_Null then @@ -3531,8 +3533,13 @@ package body Trans.Chap8 is Get_Association_Interface (El, Inter); Formal_Info : constant Ortho_Info_Acc := Get_Info (Base_Formal); begin - if Formal_Info.Interface_Field (Mode_Value) = O_Fnode_Null then + if Formal_Info.Interface_Decl (Mode_Value) /= O_Dnode_Null then -- Not a PARAMS field. + -- Note: an interface can be both a PARAMS field and an ortho + -- interface. This is the case for functions with nested + -- subprograms. At the start of those functions, the interface + -- is copied. But for a call, the actual must be passed as + -- a value of the interface. if Get_Kind (El) = Iir_Kind_Association_Element_By_Individual then -- Pass the whole data for an individual association. diff --git a/src/vhdl/translate/trans_analyzes.adb b/src/vhdl/translate/trans_analyzes.adb index d2a38d4b7..68594479c 100644 --- a/src/vhdl/translate/trans_analyzes.adb +++ b/src/vhdl/translate/trans_analyzes.adb @@ -164,7 +164,7 @@ package body Trans_Analyzes is -- (It is cleared for any statement, just to factorize code). Has_After := False; - case Iir_Kinds_Sequential_Statement (Get_Kind (Stmt)) is + case Iir_Kinds_Sequential_Statement_Ext (Get_Kind (Stmt)) is when Iir_Kind_Simple_Signal_Assignment_Statement => Extract_Driver_Simple_Signal_Assignment (Stmt); when Iir_Kind_Signal_Force_Assignment_Statement @@ -191,6 +191,8 @@ package body Trans_Analyzes is | Iir_Kind_If_Statement | Iir_Kind_Break_Statement => null; + when Iir_Kind_Suspend_State_Statement => + null; end case; return Walk_Continue; end Extract_Driver_Stmt; diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb index e4f27f32c..8429d2dab 100644 --- a/src/vhdl/vhdl-annotations.adb +++ b/src/vhdl/vhdl-annotations.adb @@ -328,8 +328,13 @@ package body Vhdl.Annotations is -- Create an annotation for the element type, as it can be -- referenced by the implicit concat function definition for -- concatenation with element. - El := Get_Element_Subtype (Def); - Annotate_Anonymous_Type_Definition (Block_Info, El); + El := Get_Element_Subtype_Indication (Def); + if Get_Kind (El) in Iir_Kinds_Subtype_Definition then + -- But only if it is a proper new subtype definition + -- (ie not a denoting name, or attributes like 'subtype). + El := Get_Element_Subtype (Def); + Annotate_Anonymous_Type_Definition (Block_Info, El); + end if; -- Then for the array. Create_Object_Info (Block_Info, Def, Kind_Type); @@ -779,7 +784,7 @@ package body Vhdl.Annotations is when Iir_Kind_Function_Declaration | Iir_Kind_Procedure_Declaration => if (Get_Implicit_Definition (Decl) - not in Iir_Predefined_Pure_Functions) + not in Iir_Predefined_Operators) and then not Is_Second_Subprogram_Specification (Decl) then Annotate_Subprogram_Interfaces_Type (Block_Info, Decl); @@ -846,6 +851,9 @@ package body Vhdl.Annotations is when Iir_Kind_Psl_Default_Clock => null; + when Iir_Kind_Suspend_State_Declaration => + Create_Object_Info (Block_Info, Decl); + when others => Error_Kind ("annotate_declaration", Decl); end case; @@ -863,10 +871,32 @@ package body Vhdl.Annotations is end loop; end Annotate_Declaration_List; + procedure Annotate_Procedure_Call_Statement + (Block_Info : Sim_Info_Acc; Stmt : Iir) + is + Call : constant Iir := Get_Procedure_Call (Stmt); + Imp : constant Iir := Get_Implementation (Call); + Assoc_Chain : constant Iir := Get_Parameter_Association_Chain (Call); + Inter_Chain : constant Iir := Get_Interface_Declaration_Chain (Imp); + Assoc : Iir; + Assoc_Inter : Iir; + Inter : Iir; + begin + Assoc := Assoc_Chain; + Assoc_Inter := Inter_Chain; + while Assoc /= Null_Iir loop + Inter := Get_Association_Interface (Assoc, Assoc_Inter); + if Is_Copyback_Parameter (Inter) then + Create_Object_Info (Block_Info, Assoc, Kind_Object); + end if; + Next_Association_Interface (Assoc, Assoc_Inter); + end loop; + end Annotate_Procedure_Call_Statement; + procedure Annotate_Sequential_Statement_Chain (Block_Info: Sim_Info_Acc; Stmt_Chain: Iir) is - El: Iir; + Stmt : Iir; Max_Nbr_Objects : Object_Slot_Type; Current_Nbr_Objects : Object_Slot_Type; @@ -884,9 +914,9 @@ package body Vhdl.Annotations is Current_Nbr_Objects := Block_Info.Nbr_Objects; Max_Nbr_Objects := Current_Nbr_Objects; - El := Stmt_Chain; - while El /= Null_Iir loop - case Get_Kind (El) is + Stmt := Stmt_Chain; + while Stmt /= Null_Iir loop + case Get_Kind (Stmt) is when Iir_Kind_Null_Statement => null; when Iir_Kind_Assertion_Statement @@ -901,7 +931,8 @@ package body Vhdl.Annotations is | Iir_Kind_Conditional_Variable_Assignment_Statement => null; when Iir_Kind_Procedure_Call_Statement => - null; + Annotate_Procedure_Call_Statement (Block_Info, Stmt); + Save_Nbr_Objects; when Iir_Kind_Exit_Statement | Iir_Kind_Next_Statement => null; @@ -910,7 +941,7 @@ package body Vhdl.Annotations is when Iir_Kind_If_Statement => declare - Clause: Iir := El; + Clause: Iir := Stmt; begin loop Annotate_Sequential_Statement_Chain @@ -925,7 +956,7 @@ package body Vhdl.Annotations is declare Assoc: Iir; begin - Assoc := Get_Case_Statement_Alternative_Chain (El); + Assoc := Get_Case_Statement_Alternative_Chain (Stmt); loop Annotate_Sequential_Statement_Chain (Block_Info, Get_Associated_Chain (Assoc)); @@ -937,21 +968,24 @@ package body Vhdl.Annotations is when Iir_Kind_For_Loop_Statement => Annotate_Declaration - (Block_Info, Get_Parameter_Specification (El)); + (Block_Info, Get_Parameter_Specification (Stmt)); Annotate_Sequential_Statement_Chain - (Block_Info, Get_Sequential_Statement_Chain (El)); + (Block_Info, Get_Sequential_Statement_Chain (Stmt)); when Iir_Kind_While_Loop_Statement => Annotate_Sequential_Statement_Chain - (Block_Info, Get_Sequential_Statement_Chain (El)); + (Block_Info, Get_Sequential_Statement_Chain (Stmt)); + + when Iir_Kind_Suspend_State_Statement => + null; when others => - Error_Kind ("annotate_sequential_statement_chain", El); + Error_Kind ("annotate_sequential_statement_chain", Stmt); end case; Save_Nbr_Objects; - El := Get_Chain (El); + Stmt := Get_Chain (Stmt); end loop; Block_Info.Nbr_Objects := Max_Nbr_Objects; end Annotate_Sequential_Statement_Chain; @@ -1114,12 +1148,22 @@ package body Vhdl.Annotations is when Iir_Kind_Concurrent_Simple_Signal_Assignment | Iir_Kind_Concurrent_Selected_Signal_Assignment | Iir_Kind_Concurrent_Conditional_Signal_Assignment - | Iir_Kind_Concurrent_Assertion_Statement - | Iir_Kind_Concurrent_Procedure_Call_Statement => + | Iir_Kind_Concurrent_Assertion_Statement => -- In case concurrent signal assignemnts were not -- canonicalized (for synthesis). null; + when Iir_Kind_Concurrent_Procedure_Call_Statement => + declare + Info : Sim_Info_Acc; + begin + Info := new Sim_Info_Type'(Kind => Kind_Process, + Ref => Stmt, + Nbr_Objects => 0); + Set_Info (Stmt, Info); + Annotate_Procedure_Call_Statement (Info, Stmt); + end; + when others => Error_Kind ("annotate_concurrent_statement", Stmt); end case; diff --git a/src/vhdl/vhdl-canon.adb b/src/vhdl/vhdl-canon.adb index d37f26493..2a8ef8aa0 100644 --- a/src/vhdl/vhdl-canon.adb +++ b/src/vhdl/vhdl-canon.adb @@ -334,7 +334,7 @@ package body Vhdl.Canon is end Canon_Extract_Sensitivity_If_Not_Null; procedure Canon_Extract_Sensitivity_Procedure_Call - (Sensitivity_List : Iir_List; Call : Iir) + (Call : Iir; Sensitivity_List : Iir_List) is Assoc : Iir; Inter : Iir; @@ -365,22 +365,76 @@ package body Vhdl.Canon is end loop; end Canon_Extract_Sensitivity_Waveform; + procedure Canon_Extract_Sensitivity_Signal_Assignment_Common + (Stmt : Iir; List : Iir_List) is + begin + Canon_Extract_Sensitivity_Expression (Get_Target (Stmt), List, True); + Canon_Extract_Sensitivity_If_Not_Null + (Get_Reject_Time_Expression (Stmt), List); + end Canon_Extract_Sensitivity_Signal_Assignment_Common; + + procedure Canon_Extract_Sensitivity_Conditional_Signal_Assignment + (Stmt : Iir; List : Iir_List) + is + Cwe : Iir; + begin + Canon_Extract_Sensitivity_Signal_Assignment_Common (Stmt, List); + Cwe := Get_Conditional_Waveform_Chain (Stmt); + while Cwe /= Null_Iir loop + Canon_Extract_Sensitivity_If_Not_Null (Get_Condition (Cwe), List); + Canon_Extract_Sensitivity_Waveform (Get_Waveform_Chain (Cwe), List); + Cwe := Get_Chain (Cwe); + end loop; + end Canon_Extract_Sensitivity_Conditional_Signal_Assignment; + + procedure Canon_Extract_Sensitivity_Simple_Signal_Assignment + (Stmt : Iir; List : Iir_List) is + begin + Canon_Extract_Sensitivity_Signal_Assignment_Common (Stmt, List); + Canon_Extract_Sensitivity_Waveform (Get_Waveform_Chain (Stmt), List); + end Canon_Extract_Sensitivity_Simple_Signal_Assignment; + + procedure Canon_Extract_Sensitivity_Selected_Signal_Assignment + (Stmt : Iir; List : Iir_List) + is + Swf : Node; + Wf : Node; + begin + Canon_Extract_Sensitivity_Signal_Assignment_Common (Stmt, List); + Canon_Extract_Sensitivity_Expression (Get_Expression (Stmt), List); + + Swf := Get_Selected_Waveform_Chain (Stmt); + while Swf /= Null_Node loop + Wf := Get_Associated_Chain (Swf); + if Wf /= Null_Iir then + Canon_Extract_Sensitivity_Waveform (Wf, List); + end if; + Swf := Get_Chain (Swf); + end loop; + end Canon_Extract_Sensitivity_Selected_Signal_Assignment; + + procedure Canon_Extract_Sensitivity_Assertion_Statement + (Stmt : Iir; List : Iir_List) is + begin + Canon_Extract_Sensitivity_Expression + (Get_Assertion_Condition (Stmt), List); + Canon_Extract_Sensitivity_If_Not_Null + (Get_Severity_Expression (Stmt), List); + Canon_Extract_Sensitivity_If_Not_Null + (Get_Report_Expression (Stmt), List); + end Canon_Extract_Sensitivity_Assertion_Statement; + procedure Canon_Extract_Sensitivity_Statement (Stmt : Iir; List : Iir_List) is begin - case Get_Kind (Stmt) is + case Iir_Kinds_Sequential_Statement_Ext (Get_Kind (Stmt)) is when Iir_Kind_Assertion_Statement => -- LRM08 11.3 -- * For each assertion, report, next, exit or return -- statement, apply the rule of 10.2 to each expression -- in the statement, and construct the union of the -- resulting sets. - Canon_Extract_Sensitivity_Expression - (Get_Assertion_Condition (Stmt), List); - Canon_Extract_Sensitivity_If_Not_Null - (Get_Severity_Expression (Stmt), List); - Canon_Extract_Sensitivity_If_Not_Null - (Get_Report_Expression (Stmt), List); + Canon_Extract_Sensitivity_Assertion_Statement (Stmt, List); when Iir_Kind_Report_Statement => -- LRM08 11.3 -- See assertion_statement case. @@ -412,29 +466,10 @@ package body Vhdl.Canon is when Iir_Kind_Simple_Signal_Assignment_Statement => -- LRM08 11.3 -- See variable assignment statement case. - Canon_Extract_Sensitivity_Expression - (Get_Target (Stmt), List, True); - Canon_Extract_Sensitivity_If_Not_Null - (Get_Reject_Time_Expression (Stmt), List); - Canon_Extract_Sensitivity_Waveform - (Get_Waveform_Chain (Stmt), List); + Canon_Extract_Sensitivity_Simple_Signal_Assignment (Stmt, List); when Iir_Kind_Conditional_Signal_Assignment_Statement => - Canon_Extract_Sensitivity_Expression - (Get_Target (Stmt), List, True); - Canon_Extract_Sensitivity_If_Not_Null - (Get_Reject_Time_Expression (Stmt), List); - declare - Cwe : Iir; - begin - Cwe := Get_Conditional_Waveform_Chain (Stmt); - while Cwe /= Null_Iir loop - Canon_Extract_Sensitivity_If_Not_Null - (Get_Condition (Cwe), List); - Canon_Extract_Sensitivity_Waveform - (Get_Waveform_Chain (Cwe), List); - Cwe := Get_Chain (Cwe); - end loop; - end; + Canon_Extract_Sensitivity_Conditional_Signal_Assignment + (Stmt, List); when Iir_Kind_If_Statement => -- LRM08 11.3 -- * For each if statement, apply the rule of 10.2 to the @@ -509,8 +544,14 @@ package body Vhdl.Canon is -- with each formal parameter of mode IN or INOUT, and -- construct the union of the resulting sets. Canon_Extract_Sensitivity_Procedure_Call - (List, Get_Procedure_Call (Stmt)); - when others => + (Get_Procedure_Call (Stmt), List); + when Iir_Kind_Selected_Waveform_Assignment_Statement + | Iir_Kind_Conditional_Variable_Assignment_Statement + | Iir_Kind_Signal_Force_Assignment_Statement + | Iir_Kind_Signal_Release_Assignment_Statement + | Iir_Kind_Break_Statement + | Iir_Kind_Wait_Statement + | Iir_Kind_Suspend_State_Statement => Error_Kind ("canon_extract_sensitivity_statement", Stmt); end case; end Canon_Extract_Sensitivity_Statement; @@ -1129,7 +1170,7 @@ package body Vhdl.Canon is -- Keep the same statement by default. N_Stmt := Stmt; - case Get_Kind (Stmt) is + case Iir_Kinds_Sequential_Statement_Ext (Get_Kind (Stmt)) is when Iir_Kind_If_Statement => declare Cond: Iir; @@ -1255,7 +1296,11 @@ package body Vhdl.Canon is when Iir_Kind_Return_Statement => Canon_Expression (Get_Expression (Stmt)); - when others => + when Iir_Kind_Selected_Waveform_Assignment_Statement + | Iir_Kind_Signal_Force_Assignment_Statement + | Iir_Kind_Signal_Release_Assignment_Statement + | Iir_Kind_Break_Statement + | Iir_Kind_Suspend_State_Statement => Error_Kind ("canon_sequential_stmts", Stmt); end case; @@ -1267,6 +1312,162 @@ package body Vhdl.Canon is return Res; end Canon_Sequential_Stmts; + function Canon_Insert_Suspend_State_Statement (Stmt : Iir; Var : Iir) + return Iir + is + Last : Iir; + Num : Int32; + Res : Iir; + begin + Res := Create_Iir (Iir_Kind_Suspend_State_Statement); + Location_Copy (Res, Stmt); + Set_Parent (Res, Get_Parent (Stmt)); + Set_Chain (Res, Stmt); + + Last := Get_Suspend_State_Chain (Var); + if Last = Null_Iir then + Num := 0; + else + Num := Get_Suspend_State_Index (Last); + end if; + + Set_Suspend_State_Index (Res, Num + 1); + Set_Suspend_State_Chain (Res, Last); + Set_Suspend_State_Chain (Var, Res); + return Res; + end Canon_Insert_Suspend_State_Statement; + + function Canon_Add_Suspend_State_Statement (First : Iir; Var : Iir) + return Iir + is + Stmt: Iir; + S_Stmt : Iir; + Res, Last : Iir; + begin + Chain_Init (Res, Last); + + Stmt := First; + while Stmt /= Null_Iir loop + + S_Stmt := Null_Iir; + + case Get_Kind (Stmt) is + when Iir_Kind_Simple_Signal_Assignment_Statement + | Iir_Kind_Conditional_Signal_Assignment_Statement => + null; + + when Iir_Kind_Variable_Assignment_Statement + | Iir_Kind_Conditional_Variable_Assignment_Statement => + null; + + when Iir_Kind_If_Statement => + if Get_Suspend_Flag (Stmt) then + declare + Clause: Iir; + Stmts : Iir; + begin + Clause := Stmt; + while Clause /= Null_Iir loop + Stmts := Get_Sequential_Statement_Chain (Clause); + Stmts := Canon_Add_Suspend_State_Statement + (Stmts, Var); + Set_Sequential_Statement_Chain (Clause, Stmts); + Clause := Get_Else_Clause (Clause); + end loop; + end; + end if; + + when Iir_Kind_Wait_Statement => + S_Stmt := Canon_Insert_Suspend_State_Statement (Stmt, Var); + + when Iir_Kind_Case_Statement => + if Get_Suspend_Flag (Stmt) then + declare + Choice: Iir; + Stmts : Iir; + begin + Choice := Get_Case_Statement_Alternative_Chain (Stmt); + while Choice /= Null_Iir loop + -- FIXME: canon choice expr. + Stmts := Get_Associated_Chain (Choice); + Stmts := Canon_Add_Suspend_State_Statement + (Stmts, Var); + Set_Associated_Chain (Choice, Stmts); + Choice := Get_Chain (Choice); + end loop; + end; + end if; + + when Iir_Kind_Assertion_Statement + | Iir_Kind_Report_Statement => + null; + + when Iir_Kind_For_Loop_Statement + | Iir_Kind_While_Loop_Statement => + if Get_Suspend_Flag (Stmt) then + declare + Stmts : Iir; + begin + Stmts := Get_Sequential_Statement_Chain (Stmt); + Stmts := Canon_Add_Suspend_State_Statement + (Stmts, Var); + Set_Sequential_Statement_Chain (Stmt, Stmts); + end; + end if; + + when Iir_Kind_Next_Statement + | Iir_Kind_Exit_Statement => + null; + + when Iir_Kind_Procedure_Call_Statement => + if Get_Suspend_Flag (Stmt) then + S_Stmt := Canon_Insert_Suspend_State_Statement (Stmt, Var); + end if; + + when Iir_Kind_Null_Statement => + null; + + when Iir_Kind_Return_Statement => + null; + + when others => + Error_Kind ("canon_add_suspend_state_statement", Stmt); + end case; + + if S_Stmt /= Null_Iir then + Chain_Append (Res, Last, S_Stmt); + end if; + Chain_Append (Res, Last, Stmt); + + Stmt := Get_Chain (Stmt); + end loop; + + return Res; + end Canon_Add_Suspend_State_Statement; + + procedure Canon_Add_Suspend_State (Proc : Iir) + is + Var : Iir; + Stmts : Iir; + begin + pragma Assert (Kind_In (Proc, Iir_Kind_Process_Statement, + Iir_Kind_Procedure_Body)); + + -- Create suspend state variable. + Var := Create_Iir (Iir_Kind_Suspend_State_Declaration); + Set_Location (Var, Get_Location (Proc)); + Set_Parent (Var, Proc); + + -- Insert it. + Set_Chain (Var, Get_Declaration_Chain (Proc)); + Set_Declaration_Chain (Proc, Var); + + -- Add suspend state statements. + Stmts := Get_Sequential_Statement_Chain (Proc); + Stmts := Canon_Add_Suspend_State_Statement (Stmts, Var); + Set_Sequential_Statement_Chain (Proc, Stmts); + end Canon_Add_Suspend_State; + -- Create a statement transform from concurrent_signal_assignment -- statement STMT (either selected or conditional). -- waveform transformation is not done. @@ -1428,7 +1629,7 @@ package body Vhdl.Canon is -- the union of the sets constructed by applying th rule of Section 8.1 -- to each actual part associated with a formal parameter. Sensitivity_List := Create_Iir_List; - Canon_Extract_Sensitivity_Procedure_Call (Sensitivity_List, Call); + Canon_Extract_Sensitivity_Procedure_Call (Call, Sensitivity_List); if Is_Sensitized then Set_Sensitivity_List (Proc, Sensitivity_List); Set_Is_Ref (Proc, True); @@ -2050,6 +2251,11 @@ package body Vhdl.Canon is when Iir_Kind_Sensitized_Process_Statement | Iir_Kind_Process_Statement => + if Canon_Flag_Add_Suspend_State + and then Get_Kind (Stmt) = Iir_Kind_Process_Statement + then + Canon_Add_Suspend_State (Stmt); + end if; Canon_Declarations (Top, Stmt, Null_Iir); if Canon_Flag_Sequentials_Stmts then declare @@ -2953,6 +3159,12 @@ package body Vhdl.Canon is when Iir_Kind_Procedure_Body | Iir_Kind_Function_Body => Canon_Declarations (Top, Decl, Null_Iir); + if Canon_Flag_Add_Suspend_State + and then Get_Kind (Decl) = Iir_Kind_Procedure_Body + and then Get_Suspend_Flag (Decl) + then + Canon_Add_Suspend_State (Decl); + end if; if Canon_Flag_Sequentials_Stmts then Stmts := Get_Sequential_Statement_Chain (Decl); Stmts := Canon_Sequential_Stmts (Stmts); @@ -3058,6 +3270,9 @@ package body Vhdl.Canon is when Iir_Kind_Psl_Default_Clock => null; + when Iir_Kind_Suspend_State_Declaration => + null; + when others => Error_Kind ("canon_declaration", Decl); end case; diff --git a/src/vhdl/vhdl-canon.ads b/src/vhdl/vhdl-canon.ads index 2c9178257..2fc6ec09a 100644 --- a/src/vhdl/vhdl-canon.ads +++ b/src/vhdl/vhdl-canon.ads @@ -32,10 +32,6 @@ package Vhdl.Canon is -- association with a non globally expression). Canon_Flag_Associations : Boolean := True; - -- If true, create a concurrent signal assignment for internal - -- associations. - Canon_Flag_Inertial_Associations : Boolean := True; - -- If true, canon lists in specifications. Canon_Flag_Specification_Lists : Boolean := True; @@ -46,6 +42,9 @@ package Vhdl.Canon is -- (If true, Canon_Flag_Sequentials_Stmts must be true) Canon_Flag_All_Sensitivity : Boolean := False; + -- Add suspend state variables and statements. + Canon_Flag_Add_Suspend_State : Boolean := False; + -- Do canonicalization: -- Transforms concurrent statements into sensitized process statements -- (all but component instanciation and block). @@ -95,4 +94,25 @@ package Vhdl.Canon is -- Used for vhdl 08. function Canon_Extract_Sensitivity_Process (Proc : Iir_Sensitized_Process_Statement) return Iir_List; + + -- For a concurrent or sequential conditional signal assignment. + procedure Canon_Extract_Sensitivity_Conditional_Signal_Assignment + (Stmt : Iir; List : Iir_List); + + -- For a concurrent or sequential simple signal assignment. + procedure Canon_Extract_Sensitivity_Simple_Signal_Assignment + (Stmt : Iir; List : Iir_List); + + -- For a concurrent selected signal statement. + procedure Canon_Extract_Sensitivity_Selected_Signal_Assignment + (Stmt : Iir; List : Iir_List); + + -- For a concurrent or sequential simple assertion statement. + procedure Canon_Extract_Sensitivity_Assertion_Statement + (Stmt : Iir; List : Iir_List); + + -- For a procedure call. + procedure Canon_Extract_Sensitivity_Procedure_Call + (Call : Iir; Sensitivity_List : Iir_List); + end Vhdl.Canon; diff --git a/src/vhdl/vhdl-elocations.adb b/src/vhdl/vhdl-elocations.adb index dbd610d3c..b428c4fab 100644 --- a/src/vhdl/vhdl-elocations.adb +++ b/src/vhdl/vhdl-elocations.adb @@ -297,6 +297,7 @@ package body Vhdl.Elocations is | Iir_Kind_Interface_Function_Declaration | Iir_Kind_Interface_Procedure_Declaration | Iir_Kind_Signal_Attribute_Declaration + | Iir_Kind_Suspend_State_Declaration | Iir_Kind_Identity_Operator | Iir_Kind_Negation_Operator | Iir_Kind_Absolute_Operator @@ -386,6 +387,7 @@ package body Vhdl.Elocations is | Iir_Kind_Exit_Statement | Iir_Kind_Procedure_Call_Statement | Iir_Kind_Break_Statement + | Iir_Kind_Suspend_State_Statement | Iir_Kind_Character_Literal | Iir_Kind_Simple_Name | Iir_Kind_Selected_Name diff --git a/src/vhdl/vhdl-elocations.ads b/src/vhdl/vhdl-elocations.ads index eaa1f78a1..810507a9f 100644 --- a/src/vhdl/vhdl-elocations.ads +++ b/src/vhdl/vhdl-elocations.ads @@ -280,6 +280,7 @@ package Vhdl.Elocations is -- Iir_Kind_Guard_Signal_Declaration (None) -- Iir_Kind_Signal_Attribute_Declaration (None) + -- Iir_Kind_Suspend_State_Declaration (None) -- Iir_Kind_Constant_Declaration (L1) -- Iir_Kind_Iterator_Declaration (L1) @@ -566,6 +567,8 @@ package Vhdl.Elocations is -- Iir_Kind_Break_Element (None) + -- Iir_Kind_Suspend_State_Statement (None) + ---------------- -- operators -- ---------------- diff --git a/src/vhdl/vhdl-errors.adb b/src/vhdl/vhdl-errors.adb index ddb2a9868..78ac59779 100644 --- a/src/vhdl/vhdl-errors.adb +++ b/src/vhdl/vhdl-errors.adb @@ -88,13 +88,6 @@ package body Vhdl.Errors is Report_Msg (Id, Elaboration, +Loc, Msg, Args); end Warning_Msg_Elab; - -- Disp a message during semantic analysis. - -- LOC is used for location and current token. - procedure Error_Msg_Sem (Msg: String; Loc: Iir) is - begin - Report_Msg (Msgid_Error, Semantic, +Get_Location_Safe (Loc), Msg); - end Error_Msg_Sem; - procedure Error_Msg_Sem (Loc: Location_Type; Msg: String; Args : Earg_Arr := No_Eargs) is @@ -495,6 +488,9 @@ package body Vhdl.Errors is when Iir_Kind_Signal_Attribute_Declaration => -- Should not appear. return "signal attribute"; + when Iir_Kind_Suspend_State_Declaration => + -- Should not appear. + return "suspend state variable"; when Iir_Kind_Group_Template_Declaration => return Disp_Identifier (Node, "group template"); when Iir_Kind_Group_Declaration => @@ -841,6 +837,9 @@ package body Vhdl.Errors is return Disp_Label (Node, "report statement"); when Iir_Kind_Break_Statement => return Disp_Label (Node, "break statement"); + when Iir_Kind_Suspend_State_Statement => + -- Should not appear. + return "suspend state statement"; when Iir_Kind_Block_Configuration => return "block configuration"; @@ -1080,8 +1079,7 @@ package body Vhdl.Errors is -- Cascade error message. return; end if; - Error_Msg_Sem ("can't match " & Disp_Node (Expr) & " with type " - & Disp_Node (A_Type), Expr); + Error_Msg_Sem (+Expr, "can't match %n with type %n", (+Expr, +A_Type)); end Error_Not_Match; function Get_Mode_Name (Mode : Iir_Mode) return String is diff --git a/src/vhdl/vhdl-evaluation.adb b/src/vhdl/vhdl-evaluation.adb index 8cb22f5c9..0cf803f97 100644 --- a/src/vhdl/vhdl-evaluation.adb +++ b/src/vhdl/vhdl-evaluation.adb @@ -858,8 +858,8 @@ package body Vhdl.Evaluation is for I in Flist_First .. Last loop -- Elements are static. Val := Get_Nth_Element (Els, I); - Write_Discrete (Res.Mem + Size_Type (I) * Typ.Vec_El.Sz, - Typ.Vec_El, Eval_Pos (Val)); + Write_Discrete (Res.Mem + Size_Type (I) * Typ.Arr_El.Sz, + Typ.Arr_El, Eval_Pos (Val)); end loop; end; when Iir_Kind_String_Literal8 => @@ -880,7 +880,7 @@ package body Vhdl.Evaluation is Lit := Get_Nth_Element (Literal_List, Natural (Str_Table.Element_String8 (Id, I))); - Write_Discrete (Res.Mem + Size_Type (I - 1), Typ.Vec_El, + Write_Discrete (Res.Mem + Size_Type (I - 1), Typ.Arr_El, Int64 (Get_Enum_Pos (Lit))); end loop; end; @@ -952,7 +952,7 @@ package body Vhdl.Evaluation is Idx_Type : Iir; begin Idx_Type := Create_Range_Subtype_From_Type (Base_Idx, Loc); - Rng := Convert_Bound_To_Node (Typ.Vbound, Base_Idx, Orig); + Rng := Convert_Bound_To_Node (Typ.Abound, Base_Idx, Orig); Set_Range_Constraint (Idx_Type, Rng); Res := Create_Array_Subtype (Btype, Loc); @@ -976,7 +976,7 @@ package body Vhdl.Evaluation is Literal_List : constant Iir_Flist := Get_Enumeration_Literal_List (Element_Type); - Len : constant Nat32 := Nat32 (Mt.Typ.Vbound.Len); + Len : constant Nat32 := Nat32 (Mt.Typ.Abound.Len); List : Iir_Flist; El : Int64; @@ -986,7 +986,7 @@ package body Vhdl.Evaluation is for I in 1 .. Len loop El := Read_Discrete (Mt.Mem + Size_Type (I - 1), - Mt.Typ.Vec_El); + Mt.Typ.Arr_El); Lit := Get_Nth_Element (Literal_List, Natural (El)); Set_Nth_Element (List, Natural (I - 1), Lit); end loop; @@ -2585,8 +2585,7 @@ package body Vhdl.Evaluation is | Iir_Predefined_Bit_Array_Match_Inequality | Iir_Predefined_Std_Ulogic_Array_Match_Equality | Iir_Predefined_Std_Ulogic_Array_Match_Inequality => - -- TODO - raise Internal_Error; + return Eval_Ieee_Operator (Orig, Imp, Left, Right); when Iir_Predefined_Enum_To_String | Iir_Predefined_Integer_To_String @@ -4061,23 +4060,24 @@ package body Vhdl.Evaluation is end if; end Eval_Expr_Check_If_Static; - function Eval_Int_In_Range (Val : Int64; Bound : Iir) return Boolean is + function Eval_Int_In_Range (Val : Int64; Bound : Iir) return Boolean + is + L, R : Iir; begin case Get_Kind (Bound) is when Iir_Kind_Range_Expression => + L := Get_Left_Limit (Bound); + R := Get_Right_Limit (Bound); + if Get_Kind (L) = Iir_Kind_Overflow_Literal + or else Get_Kind (R) = Iir_Kind_Overflow_Literal + then + return True; + end if; case Get_Direction (Bound) is when Dir_To => - if Val < Eval_Pos (Get_Left_Limit (Bound)) - or else Val > Eval_Pos (Get_Right_Limit (Bound)) - then - return False; - end if; + return Val >= Eval_Pos (L) and then Val <= Eval_Pos (R); when Dir_Downto => - if Val > Eval_Pos (Get_Left_Limit (Bound)) - or else Val < Eval_Pos (Get_Right_Limit (Bound)) - then - return False; - end if; + return Val <= Eval_Pos (L) and then Val >= Eval_Pos (R); end case; when others => Error_Kind ("eval_int_in_range", Bound); diff --git a/src/vhdl/vhdl-ieee-math_real.adb b/src/vhdl/vhdl-ieee-math_real.adb index d11030d49..d52b8ae85 100644 --- a/src/vhdl/vhdl-ieee-math_real.adb +++ b/src/vhdl/vhdl-ieee-math_real.adb @@ -16,11 +16,13 @@ with Std_Names; use Std_Names; +with Vhdl.Std_Package; + package body Vhdl.Ieee.Math_Real is procedure Extract_Declarations (Pkg : Iir_Package_Declaration) is Decl : Iir; - Predef : Iir_Predefined_Functions; + Def : Iir_Predefined_Functions; begin Math_Real_Pkg := Pkg; @@ -36,28 +38,43 @@ package body Vhdl.Ieee.Math_Real is case Get_Kind (Decl) is when Iir_Kind_Function_Declaration => - Predef := Iir_Predefined_None; + Def := Iir_Predefined_None; case Get_Identifier (Decl) is + when Name_Sign => + Def := Iir_Predefined_Ieee_Math_Real_Sign; + when Name_Mod => + Def := Iir_Predefined_Ieee_Math_Real_Mod; when Name_Ceil => - Predef := Iir_Predefined_Ieee_Math_Real_Ceil; + Def := Iir_Predefined_Ieee_Math_Real_Ceil; when Name_Floor => - Predef := Iir_Predefined_Ieee_Math_Real_Floor; + Def := Iir_Predefined_Ieee_Math_Real_Floor; when Name_Round => - Predef := Iir_Predefined_Ieee_Math_Real_Round; + Def := Iir_Predefined_Ieee_Math_Real_Round; when Name_Log2 => - Predef := Iir_Predefined_Ieee_Math_Real_Log2; + Def := Iir_Predefined_Ieee_Math_Real_Log2; when Name_Sin => - Predef := Iir_Predefined_Ieee_Math_Real_Sin; + Def := Iir_Predefined_Ieee_Math_Real_Sin; when Name_Cos => - Predef := Iir_Predefined_Ieee_Math_Real_Cos; + Def := Iir_Predefined_Ieee_Math_Real_Cos; when Name_Arctan => - Predef := Iir_Predefined_Ieee_Math_Real_Arctan; + Def := Iir_Predefined_Ieee_Math_Real_Arctan; when Name_Op_Exp => - Predef := Iir_Predefined_Ieee_Math_Real_Pow; + declare + use Vhdl.Std_Package; + Inter : constant Iir := + Get_Interface_Declaration_Chain (Decl); + Itype : constant Iir := Get_Type (Inter); + begin + if Itype = Integer_Subtype_Definition then + Def := Iir_Predefined_Ieee_Math_Real_Pow_Int_Real; + elsif Itype = Real_Subtype_Definition then + Def := Iir_Predefined_Ieee_Math_Real_Pow_Real_Real; + end if; + end; when others => null; end case; - Set_Implicit_Definition (Decl, Predef); + Set_Implicit_Definition (Decl, Def); when Iir_Kind_Constant_Declaration => null; when others => diff --git a/src/vhdl/vhdl-ieee-numeric.adb b/src/vhdl/vhdl-ieee-numeric.adb index 2e26eb187..3a77bd0e8 100644 --- a/src/vhdl/vhdl-ieee-numeric.adb +++ b/src/vhdl/vhdl-ieee-numeric.adb @@ -466,9 +466,13 @@ package body Vhdl.Ieee.Numeric is (Pkg_Std => (Type_Unsigned => (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_And_Uns_Uns, + Arg_Vect_Log => Iir_Predefined_Ieee_Numeric_Std_And_Uns_Log, + Arg_Log_Vect => Iir_Predefined_Ieee_Numeric_Std_And_Log_Uns, others => Iir_Predefined_None), Type_Signed => (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_And_Sgn_Sgn, + Arg_Vect_Log => Iir_Predefined_Ieee_Numeric_Std_And_Sgn_Log, + Arg_Log_Vect => Iir_Predefined_Ieee_Numeric_Std_And_Log_Sgn, others => Iir_Predefined_None)), Pkg_Bit => (others => @@ -478,9 +482,13 @@ package body Vhdl.Ieee.Numeric is (Pkg_Std => (Type_Unsigned => (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Or_Uns_Uns, + Arg_Vect_Log => Iir_Predefined_Ieee_Numeric_Std_Or_Uns_Log, + Arg_Log_Vect => Iir_Predefined_Ieee_Numeric_Std_Or_Log_Uns, others => Iir_Predefined_None), Type_Signed => (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Or_Sgn_Sgn, + Arg_Vect_Log => Iir_Predefined_Ieee_Numeric_Std_Or_Sgn_Log, + Arg_Log_Vect => Iir_Predefined_Ieee_Numeric_Std_Or_Log_Sgn, others => Iir_Predefined_None)), Pkg_Bit => (others => @@ -490,9 +498,13 @@ package body Vhdl.Ieee.Numeric is (Pkg_Std => (Type_Unsigned => (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Nand_Uns_Uns, + Arg_Vect_Log => Iir_Predefined_Ieee_Numeric_Std_Nand_Uns_Log, + Arg_Log_Vect => Iir_Predefined_Ieee_Numeric_Std_Nand_Log_Uns, others => Iir_Predefined_None), Type_Signed => (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Nand_Sgn_Sgn, + Arg_Vect_Log => Iir_Predefined_Ieee_Numeric_Std_Nand_Sgn_Log, + Arg_Log_Vect => Iir_Predefined_Ieee_Numeric_Std_Nand_Log_Sgn, others => Iir_Predefined_None)), Pkg_Bit => (others => @@ -502,9 +514,13 @@ package body Vhdl.Ieee.Numeric is (Pkg_Std => (Type_Unsigned => (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Nor_Uns_Uns, + Arg_Vect_Log => Iir_Predefined_Ieee_Numeric_Std_Nor_Uns_Log, + Arg_Log_Vect => Iir_Predefined_Ieee_Numeric_Std_Nor_Log_Uns, others => Iir_Predefined_None), Type_Signed => (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Nor_Sgn_Sgn, + Arg_Vect_Log => Iir_Predefined_Ieee_Numeric_Std_Nor_Sgn_Log, + Arg_Log_Vect => Iir_Predefined_Ieee_Numeric_Std_Nor_Log_Sgn, others => Iir_Predefined_None)), Pkg_Bit => (others => @@ -514,9 +530,13 @@ package body Vhdl.Ieee.Numeric is (Pkg_Std => (Type_Unsigned => (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Xor_Uns_Uns, + Arg_Vect_Log => Iir_Predefined_Ieee_Numeric_Std_Xor_Uns_Log, + Arg_Log_Vect => Iir_Predefined_Ieee_Numeric_Std_Xor_Log_Uns, others => Iir_Predefined_None), Type_Signed => (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Xor_Sgn_Sgn, + Arg_Vect_Log => Iir_Predefined_Ieee_Numeric_Std_Xor_Sgn_Log, + Arg_Log_Vect => Iir_Predefined_Ieee_Numeric_Std_Xor_Log_Sgn, others => Iir_Predefined_None)), Pkg_Bit => (others => @@ -526,9 +546,13 @@ package body Vhdl.Ieee.Numeric is (Pkg_Std => (Type_Unsigned => (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Xnor_Uns_Uns, + Arg_Vect_Log => Iir_Predefined_Ieee_Numeric_Std_Xnor_Uns_Log, + Arg_Log_Vect => Iir_Predefined_Ieee_Numeric_Std_Xnor_Log_Uns, others => Iir_Predefined_None), Type_Signed => (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Xnor_Sgn_Sgn, + Arg_Vect_Log => Iir_Predefined_Ieee_Numeric_Std_Xnor_Sgn_Log, + Arg_Log_Vect => Iir_Predefined_Ieee_Numeric_Std_Xnor_Log_Sgn, others => Iir_Predefined_None)), Pkg_Bit => (others => @@ -582,6 +606,34 @@ package body Vhdl.Ieee.Numeric is (Type_Signed => Iir_Predefined_Ieee_Numeric_Std_Find_Rightmost_Sgn, Type_Unsigned => Iir_Predefined_Ieee_Numeric_Std_Find_Rightmost_Uns); + To_01_Patterns : constant Shift_Pattern_Type := + (Type_Signed => Iir_Predefined_Ieee_Numeric_Std_To_01_Sgn, + Type_Unsigned => Iir_Predefined_Ieee_Numeric_Std_To_01_Uns); + + To_X01_Patterns : constant Shift_Pattern_Type := + (Type_Signed => Iir_Predefined_Ieee_Numeric_Std_To_X01_Sgn, + Type_Unsigned => Iir_Predefined_Ieee_Numeric_Std_To_X01_Uns); + + To_X01z_Patterns : constant Shift_Pattern_Type := + (Type_Signed => Iir_Predefined_Ieee_Numeric_Std_To_X01Z_Sgn, + Type_Unsigned => Iir_Predefined_Ieee_Numeric_Std_To_X01Z_Uns); + + To_Ux01_Patterns : constant Shift_Pattern_Type := + (Type_Signed => Iir_Predefined_Ieee_Numeric_Std_To_UX01_Sgn, + Type_Unsigned => Iir_Predefined_Ieee_Numeric_Std_To_UX01_Uns); + + Is_X_Patterns : constant Shift_Pattern_Type := + (Type_Signed => Iir_Predefined_Ieee_Numeric_Std_Is_X_Sgn, + Type_Unsigned => Iir_Predefined_Ieee_Numeric_Std_Is_X_Uns); + + To_Hstring_Patterns : constant Shift_Pattern_Type := + (Type_Signed => Iir_Predefined_Ieee_Numeric_Std_To_Hstring_Sgn, + Type_Unsigned => Iir_Predefined_Ieee_Numeric_Std_To_Hstring_Uns); + + To_Ostring_Patterns : constant Shift_Pattern_Type := + (Type_Signed => Iir_Predefined_Ieee_Numeric_Std_To_Ostring_Sgn, + Type_Unsigned => Iir_Predefined_Ieee_Numeric_Std_To_Ostring_Uns); + Error : exception; procedure Extract_Declarations (Pkg_Decl : Iir_Package_Declaration; @@ -618,6 +670,9 @@ package body Vhdl.Ieee.Numeric is elsif Arg_Type = Ieee.Std_Logic_1164.Std_Logic_Vector_Type then Sign := Type_Slv; Kind := Arg_Vect; + elsif Arg_Type = Vhdl.Std_Package.Bit_Type_Definition then + Sign := Type_Log; + Kind := Arg_Scal; else raise Error; end if; @@ -667,21 +722,36 @@ package body Vhdl.Ieee.Numeric is Set_Implicit_Definition (Decl, Pats (Pkg, Arg1_Sign)); end Handle_Unary; - procedure Handle_To_Unsigned is + procedure Handle_To_Unsigned + is + Predefined : Iir_Predefined_Functions; begin if Arg1_Kind = Arg_Scal and Arg1_Sign = Type_Unsigned then if Arg2_Kind = Arg_Scal and Arg2_Sign = Type_Unsigned then - Set_Implicit_Definition - (Decl, Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Nat_Uns); + case Pkg is + when Pkg_Std => + Predefined := + Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Nat_Uns; + when Pkg_Bit => + Predefined := + Iir_Predefined_Ieee_Numeric_Bit_Touns_Nat_Nat_Uns; + end case; elsif Arg2_Kind = Arg_Vect and Arg2_Sign = Type_Unsigned then - Set_Implicit_Definition - (Decl, Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Uns_Uns); + case Pkg is + when Pkg_Std => + Predefined := + Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Uns_Uns; + when Pkg_Bit => + Predefined := + Iir_Predefined_Ieee_Numeric_Bit_Touns_Nat_Uns_Uns; + end case; else raise Error; end if; else raise Error; end if; + Set_Implicit_Definition (Decl, Predefined); end Handle_To_Unsigned; procedure Handle_To_Signed is @@ -786,18 +856,20 @@ package body Vhdl.Ieee.Numeric is raise Error; end if; - case Arg1_Sign is - when Type_Unsigned => - Predefined := Iir_Predefined_Ieee_Numeric_Std_To_01_Uns; - when Type_Signed => - Predefined := Iir_Predefined_Ieee_Numeric_Std_To_01_Sgn; - when others => - raise Error; - end case; + Predefined := To_01_Patterns (Arg1_Sign); Set_Implicit_Definition (Decl, Predefined); end Handle_To_01; + procedure Handle_To_X01 (Pats : Shift_Pattern_Type) is + begin + if Arg1_Kind /= Arg_Vect then + raise Error; + end if; + + Set_Implicit_Definition (Decl, Pats (Arg1_Sign)); + end Handle_To_X01; + procedure Handle_Shift (Pats : Shift_Pattern_Type; Sh_Sign : Sign_Kind) is Res : Iir_Predefined_Functions; @@ -955,10 +1027,6 @@ package body Vhdl.Ieee.Numeric is Handle_Binary (Xor_Patterns); when Name_Xnor => Handle_Binary (Xnor_Patterns); - when Name_To_Bstring - | Name_To_Ostring - | Name_To_Hstring => - null; when Name_To_Unsigned => Handle_To_Unsigned; when Name_To_Signed => @@ -1019,6 +1087,20 @@ package body Vhdl.Ieee.Numeric is Handle_Unary (Red_Xor_Patterns); when Name_Xnor => Handle_Unary (Red_Xnor_Patterns); + when Name_To_X01 => + Handle_To_X01 (To_X01_Patterns); + when Name_To_X01Z => + Handle_To_X01 (To_X01z_Patterns); + when Name_To_UX01 => + Handle_To_X01 (To_Ux01_Patterns); + when Name_Is_X => + Handle_To_X01 (Is_X_Patterns); + when Name_To_Bstring => + null; + when Name_To_Ostring => + Handle_To_X01 (To_Ostring_Patterns); + when Name_To_Hstring => + Handle_To_X01 (To_Hstring_Patterns); when others => null; end case; @@ -1048,4 +1130,18 @@ package body Vhdl.Ieee.Numeric is Numeric_Std_Unsigned_Type := Null_Iir; Numeric_Std_Signed_Type := Null_Iir; end Extract_Std_Declarations; + + procedure Extract_Bit_Declarations (Pkg : Iir_Package_Declaration) is + begin + Numeric_Bit_Pkg := Pkg; + + Extract_Declarations + (Pkg, Pkg_Bit, Numeric_Bit_Unsigned_Type, Numeric_Bit_Signed_Type); + exception + when Error => + Error_Msg_Sem (+Pkg, "package ieee.numeric_bit is ill-formed"); + Numeric_Bit_Pkg := Null_Iir; + Numeric_Bit_Unsigned_Type := Null_Iir; + Numeric_Bit_Signed_Type := Null_Iir; + end Extract_Bit_Declarations; end Vhdl.Ieee.Numeric; diff --git a/src/vhdl/vhdl-ieee-numeric.ads b/src/vhdl/vhdl-ieee-numeric.ads index 6a329d07c..7b2a7ae8c 100644 --- a/src/vhdl/vhdl-ieee-numeric.ads +++ b/src/vhdl/vhdl-ieee-numeric.ads @@ -19,6 +19,13 @@ package Vhdl.Ieee.Numeric is Numeric_Std_Unsigned_Type : Iir_Array_Type_Definition := Null_Iir; Numeric_Std_Signed_Type : Iir_Array_Type_Definition := Null_Iir; + Numeric_Bit_Pkg : Iir_Package_Declaration := Null_Iir; + Numeric_Bit_Unsigned_Type : Iir_Array_Type_Definition := Null_Iir; + Numeric_Bit_Signed_Type : Iir_Array_Type_Definition := Null_Iir; + -- Extract declarations from PKG (ieee.numeric_std). procedure Extract_Std_Declarations (Pkg : Iir_Package_Declaration); + + -- Extract declarations from PKG (ieee.numeric_bit). + procedure Extract_Bit_Declarations (Pkg : Iir_Package_Declaration); end Vhdl.Ieee.Numeric; diff --git a/src/vhdl/vhdl-ieee-numeric_std_unsigned.adb b/src/vhdl/vhdl-ieee-numeric_std_unsigned.adb index 7d8edbb96..06baad51d 100644 --- a/src/vhdl/vhdl-ieee-numeric_std_unsigned.adb +++ b/src/vhdl/vhdl-ieee-numeric_std_unsigned.adb @@ -55,10 +55,65 @@ package body Vhdl.Ieee.Numeric_Std_Unsigned is Classify_Arg (Arg1, Arg1_Kind); Classify_Arg (Arg2, Arg2_Kind); case Get_Identifier (Decl) is + when Name_Op_Plus => + if Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Slv then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Add_Slv_Slv; + elsif Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Int then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Add_Slv_Nat; + elsif Arg1_Kind = Arg_Int and Arg2_Kind = Arg_Slv then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Add_Nat_Slv; + end if; + when Name_Op_Minus => + if Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Slv then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Sub_Slv_Slv; + elsif Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Int then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Sub_Slv_Nat; + elsif Arg1_Kind = Arg_Int and Arg2_Kind = Arg_Slv then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Sub_Nat_Slv; + end if; when Name_To_Stdlogicvector => if Arg1_Kind = Arg_Int and Arg2_Kind = Arg_Int then - Res := - Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Nat_Slv; + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Nat; + elsif Arg1_Kind = Arg_Int and Arg2_Kind = Arg_Slv then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Slv; + end if; + when Name_To_Stdulogicvector => + if Arg1_Kind = Arg_Int and Arg2_Kind = Arg_Int then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Suv_Nat_Nat; + elsif Arg1_Kind = Arg_Int and Arg2_Kind = Arg_Slv then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Suv_Nat_Suv; + end if; + when Name_Resize => + if Arg2_Kind = Arg_Int then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Resize_Slv_Nat; + elsif Arg2_Kind = Arg_Slv then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Resize_Slv_Slv; + end if; + when Name_Find_Leftmost => + pragma Assert (Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Log); + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Find_Leftmost; + when Name_Find_Rightmost => + pragma Assert (Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Log); + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Find_Rightmost; + when Name_Shift_Left => + pragma Assert (Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Int); + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Shift_Left; + when Name_Shift_Right => + pragma Assert (Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Int); + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Shift_Right; + when Name_Rotate_Left => + pragma Assert (Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Int); + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Rotate_Left; + when Name_Rotate_Right => + pragma Assert (Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Int); + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Rotate_Right; + when Name_Maximum => + if Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Slv then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Maximum_Slv_Slv; + end if; + when Name_Minimum => + if Arg1_Kind = Arg_Slv and Arg2_Kind = Arg_Slv then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Minimum_Slv_Slv; end if; when others => null; diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb index 43c20dc79..207d2f0c5 100644 --- a/src/vhdl/vhdl-ieee-std_logic_1164.adb +++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb @@ -369,6 +369,13 @@ package body Vhdl.Ieee.Std_Logic_1164 is Predefined := Iir_Predefined_Ieee_1164_To_Stdulogicvector_Bv; end if; + when Name_To_01 => + if Is_Suv_Log_Function (Decl) then + -- TODO: distinguish slv/suv. + Predefined := Iir_Predefined_Ieee_1164_To_01_Slv_Log; + elsif Is_Scalar_Scalar_Function (Decl) then + Predefined := Iir_Predefined_Ieee_1164_To_01_Log_Log; + end if; when Name_To_X01 => if Is_Vector_Function (Decl) then -- TODO: distinguish slv/suv. @@ -376,6 +383,24 @@ package body Vhdl.Ieee.Std_Logic_1164 is elsif Is_Scalar_Function (Decl) then Predefined := Iir_Predefined_Ieee_1164_To_X01_Log; end if; + when Name_To_UX01 => + if Is_Vector_Function (Decl) then + -- TODO: distinguish slv/suv. + Predefined := Iir_Predefined_Ieee_1164_To_UX01_Slv; + elsif Is_Scalar_Function (Decl) then + Predefined := Iir_Predefined_Ieee_1164_To_UX01_Log; + end if; + when Name_To_X01Z => + if Is_Vector_Function (Decl) then + -- TODO: distinguish slv/suv. + Predefined := Iir_Predefined_Ieee_1164_To_X01Z_Slv; + elsif Is_Scalar_Function (Decl) then + Predefined := Iir_Predefined_Ieee_1164_To_X01Z_Log; + end if; + when Name_To_Hstring => + Predefined := Iir_Predefined_Ieee_1164_To_Hstring; + when Name_To_Ostring => + Predefined := Iir_Predefined_Ieee_1164_To_Ostring; when others => if Is_Scalar_Scalar_Function (Decl) then case Get_Identifier (Decl) is @@ -402,8 +427,7 @@ package body Vhdl.Ieee.Std_Logic_1164 is Predefined := Iir_Predefined_Ieee_1164_Condition_Operator; when Name_Is_X => - Predefined := - Iir_Predefined_Ieee_1164_Scalar_Is_X; + Predefined := Iir_Predefined_Ieee_1164_Is_X_Log; when others => Predefined := Iir_Predefined_None; end case; @@ -441,8 +465,7 @@ package body Vhdl.Ieee.Std_Logic_1164 is when Name_Xnor => Predefined := Iir_Predefined_Ieee_1164_Xnor_Suv; when Name_Is_X => - Predefined := - Iir_Predefined_Ieee_1164_Scalar_Is_X; + Predefined := Iir_Predefined_Ieee_1164_Is_X_Slv; when others => Predefined := Iir_Predefined_None; end case; diff --git a/src/vhdl/vhdl-nodes.adb b/src/vhdl/vhdl-nodes.adb index 947cd771d..b2946d62c 100644 --- a/src/vhdl/vhdl-nodes.adb +++ b/src/vhdl/vhdl-nodes.adb @@ -1083,6 +1083,7 @@ package body Vhdl.Nodes is | Iir_Kind_Interface_Terminal_Declaration | Iir_Kind_Interface_Type_Declaration | Iir_Kind_Signal_Attribute_Declaration + | Iir_Kind_Suspend_State_Declaration | Iir_Kind_Identity_Operator | Iir_Kind_Negation_Operator | Iir_Kind_Absolute_Operator @@ -1177,6 +1178,7 @@ package body Vhdl.Nodes is | Iir_Kind_Procedure_Call_Statement | Iir_Kind_Break_Statement | Iir_Kind_If_Statement + | Iir_Kind_Suspend_State_Statement | Iir_Kind_Elsif | Iir_Kind_Character_Literal | Iir_Kind_Simple_Name @@ -6072,6 +6074,22 @@ package body Vhdl.Nodes is Set_Flag4 (Name, Flag); end Set_In_Formal_Flag; + function Get_Inertial_Flag (Name : Iir) return Boolean is + begin + pragma Assert (Name /= Null_Iir); + pragma Assert (Has_Inertial_Flag (Get_Kind (Name)), + "no field Inertial_Flag"); + return Get_Flag5 (Name); + end Get_Inertial_Flag; + + procedure Set_Inertial_Flag (Name : Iir; Flag : Boolean) is + begin + pragma Assert (Name /= Null_Iir); + pragma Assert (Has_Inertial_Flag (Get_Kind (Name)), + "no field Inertial_Flag"); + Set_Flag5 (Name, Flag); + end Set_Inertial_Flag; + function Get_Slice_Subtype (Slice : Iir) return Iir is begin pragma Assert (Slice /= Null_Iir); @@ -7408,4 +7426,36 @@ package body Vhdl.Nodes is Set_Field1 (N, Int32_To_Iir (En)); end Set_Foreign_Node; + function Get_Suspend_State_Index (N : Iir) return Int32 is + begin + pragma Assert (N /= Null_Iir); + pragma Assert (Has_Suspend_State_Index (Get_Kind (N)), + "no field Suspend_State_Index"); + return Iir_To_Int32 (Get_Field3 (N)); + end Get_Suspend_State_Index; + + procedure Set_Suspend_State_Index (N : Iir; Num : Int32) is + begin + pragma Assert (N /= Null_Iir); + pragma Assert (Has_Suspend_State_Index (Get_Kind (N)), + "no field Suspend_State_Index"); + Set_Field3 (N, Int32_To_Iir (Num)); + end Set_Suspend_State_Index; + + function Get_Suspend_State_Chain (N : Iir) return Iir is + begin + pragma Assert (N /= Null_Iir); + pragma Assert (Has_Suspend_State_Chain (Get_Kind (N)), + "no field Suspend_State_Chain"); + return Get_Field4 (N); + end Get_Suspend_State_Chain; + + procedure Set_Suspend_State_Chain (N : Iir; Chain : Iir) is + begin + pragma Assert (N /= Null_Iir); + pragma Assert (Has_Suspend_State_Chain (Get_Kind (N)), + "no field Suspend_State_Chain"); + Set_Field4 (N, Chain); + end Set_Suspend_State_Chain; + end Vhdl.Nodes; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 1e97286d0..4a9fc797f 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -485,6 +485,10 @@ package Vhdl.Nodes is -- -- Get/Set_In_Formal_Flag (Flag4) -- + -- Only for Iir_Kind_Association_Element_By_Expression: + -- True for inertial associations (even without the inertial word). + -- Get/Set_Inertial_Flag (Flag5) + -- -- Only for Iir_Kind_Association_Element_By_Individual: -- Must be Locally unless there is an error on one choice. -- Get/Set_Choice_Staticness (State1) @@ -901,6 +905,10 @@ package Vhdl.Nodes is -- Get/Set_Type_Marks_List (Field2) -- -- Get/Set_Return_Type_Mark (Field8) + -- + -- Get/Set_Named_Entity (Field4) + -- + -- Get/Set_Is_Forward_Ref (Flag1) -- Iir_Kind_Overload_List (Short) -- @@ -1602,12 +1610,14 @@ package Vhdl.Nodes is -- -- Get/Set_Implicit_Definition (Field7) -- + -- Only for Iir_Kind_Function_Declaration: -- Get/Set_Return_Type_Mark (Field8) -- -- Get/Set_Subprogram_Body (Field9) -- -- Get/Set_Subprogram_Depth (Field10) -- + -- Only for Iir_Kind_Function_Declaration: -- Get/Set_Return_Identifier (Field11) -- -- Get/Set_Overload_Number (Field12) @@ -1872,6 +1882,17 @@ package Vhdl.Nodes is -- Chain of signals -- Get/Set_Signal_Attribute_Chain (Field3) + -- Iir_Kind_Suspend_State_Declaration (Short) + -- + -- Implicit state variable to handle suspension. Added after semantic + -- analysis. + -- + -- Get/Set_Parent (Field0) + -- + -- Get/Set_Chain (Field2) + -- + -- Get/Set_Suspend_State_Chain (Field4) + -- Iir_Kind_Constant_Declaration (Medium) -- Iir_Kind_Iterator_Declaration (Short) -- @@ -2692,6 +2713,9 @@ package Vhdl.Nodes is -- Get/Set_Has_Signal_Flag (Flag3) -- Iir_Kind_Protected_Type_Declaration (Short) + -- The parent of a protected type declarationi s the same parent as the + -- type declaration. + -- Get/Set_Parent (Field0) -- -- Get/Set_Declaration_Chain (Field1) -- @@ -4122,6 +4146,19 @@ package Vhdl.Nodes is -- -- Get/Set_Expression (Field5) + -- Iir_Kind_Suspend_State_Statement (Short) + -- + -- Implicit statement added to mark a suspend point. + -- + -- Get/Set_Parent (Field0) + -- + -- Next statement + -- Get/Set_Chain (Field2) + -- + -- Get/Set_Suspend_State_Index (Field3) + -- + -- Get/Set_Suspend_State_Chain (Field4) + ---------------- -- operators -- ---------------- @@ -4998,6 +5035,7 @@ package Vhdl.Nodes is Iir_Kind_Interface_Procedure_Declaration, -- interface Iir_Kind_Signal_Attribute_Declaration, + Iir_Kind_Suspend_State_Declaration, -- Expressions. Iir_Kind_Identity_Operator, @@ -5117,6 +5155,7 @@ package Vhdl.Nodes is Iir_Kind_Procedure_Call_Statement, Iir_Kind_Break_Statement, Iir_Kind_If_Statement, + Iir_Kind_Suspend_State_Statement, Iir_Kind_Elsif, -- Names @@ -5291,11 +5330,6 @@ package Vhdl.Nodes is Iir_Predefined_Enum_Greater, Iir_Predefined_Enum_Greater_Equal, - -- LRM08 5.2.6 Predefined operations on scalar types. - Iir_Predefined_Enum_Minimum, - Iir_Predefined_Enum_Maximum, - Iir_Predefined_Enum_To_String, - -- Predefined operators for BIT type. -- LRM08 9.2.2 Logical Operators @@ -5318,10 +5352,6 @@ package Vhdl.Nodes is -- LRM08 9.2.9 Condition operator Iir_Predefined_Bit_Condition, - -- LRM08 5.2.6 Predefined operations on scalar types. - Iir_Predefined_Bit_Rising_Edge, - Iir_Predefined_Bit_Falling_Edge, - -- Predefined operators for any integer type. -- LRM08 9.2.3 Relational Operators @@ -5352,11 +5382,6 @@ package Vhdl.Nodes is -- LRM08 9.2.8 Miscellaneous operators Iir_Predefined_Integer_Exp, - -- LRM08 5.2.6 Predefined operations on scalar types. - Iir_Predefined_Integer_Minimum, - Iir_Predefined_Integer_Maximum, - Iir_Predefined_Integer_To_String, - -- Predefined operators for any floating type. -- LRM08 9.2.3 Relational Operators @@ -5385,13 +5410,6 @@ package Vhdl.Nodes is -- LRM08 9.2.8 Miscellaneous operators Iir_Predefined_Floating_Exp, - -- LRM08 5.2.6 Predefined operations on scalar types. - Iir_Predefined_Floating_Minimum, - Iir_Predefined_Floating_Maximum, - Iir_Predefined_Floating_To_String, - Iir_Predefined_Real_To_String_Digits, - Iir_Predefined_Real_To_String_Format, - -- Predefined operator for universal types. -- LRM08 9.2.7 Multiplying operators @@ -5431,12 +5449,6 @@ package Vhdl.Nodes is Iir_Predefined_Physical_Mod, Iir_Predefined_Physical_Rem, - -- LRM08 5.2.6 Predefined operations on scalar types. - Iir_Predefined_Physical_Minimum, - Iir_Predefined_Physical_Maximum, - Iir_Predefined_Physical_To_String, - Iir_Predefined_Time_To_String_Unit, - -- Predefined operators for access. -- LRM08 9.2.3 Relational Operators @@ -5519,11 +5531,6 @@ package Vhdl.Nodes is Iir_Predefined_Bit_Array_Match_Equality, Iir_Predefined_Bit_Array_Match_Inequality, - -- LRM08 5.3.2.4 Predefined operations on array types - Iir_Predefined_Array_Char_To_String, - Iir_Predefined_Bit_Vector_To_Ostring, - Iir_Predefined_Bit_Vector_To_Hstring, - -- LRM08 9.2.3 Relational Operators -- IEEE.Std_Logic_1164.Std_Ulogic Iir_Predefined_Std_Ulogic_Match_Equality, @@ -5537,6 +5544,38 @@ package Vhdl.Nodes is Iir_Predefined_Std_Ulogic_Array_Match_Equality, Iir_Predefined_Std_Ulogic_Array_Match_Inequality, + -- LRM08 5.2.6 Predefined operations on scalar types. + Iir_Predefined_Enum_Minimum, + Iir_Predefined_Enum_Maximum, + Iir_Predefined_Enum_To_String, + + -- LRM08 5.2.6 Predefined operations on scalar types. + Iir_Predefined_Integer_Minimum, + Iir_Predefined_Integer_Maximum, + Iir_Predefined_Integer_To_String, + + -- LRM08 5.2.6 Predefined operations on scalar types. + Iir_Predefined_Bit_Rising_Edge, + Iir_Predefined_Bit_Falling_Edge, + + -- LRM08 5.2.6 Predefined operations on scalar types. + Iir_Predefined_Floating_Minimum, + Iir_Predefined_Floating_Maximum, + Iir_Predefined_Floating_To_String, + Iir_Predefined_Real_To_String_Digits, + Iir_Predefined_Real_To_String_Format, + + -- LRM08 5.2.6 Predefined operations on scalar types. + Iir_Predefined_Physical_Minimum, + Iir_Predefined_Physical_Maximum, + Iir_Predefined_Physical_To_String, + Iir_Predefined_Time_To_String_Unit, + + -- LRM08 5.3.2.4 Predefined operations on array types + Iir_Predefined_Array_Char_To_String, + Iir_Predefined_Bit_Vector_To_Ostring, + Iir_Predefined_Bit_Vector_To_Hstring, + -- -- Predefined attribute functions. -- Iir_Predefined_Attribute_Image, -- Iir_Predefined_Attribute_Value, @@ -5584,6 +5623,13 @@ package Vhdl.Nodes is Iir_Predefined_Foreign_Textio_Read_Real, Iir_Predefined_Foreign_Textio_Write_Real, + -- Defined in package std.env + Iir_Predefined_Std_Env_Stop_Status, + Iir_Predefined_Std_Env_Stop, + Iir_Predefined_Std_Env_Finish_Status, + Iir_Predefined_Std_Env_Finish, + Iir_Predefined_Std_Env_Resolution_Limit, + -- Defined in package ieee.std_logic_1164 -- Std_Ulogic operations. @@ -5634,8 +5680,8 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_1164_To_UX01_Bv_Suv, Iir_Predefined_Ieee_1164_To_UX01_Bit_Log, - Iir_Predefined_Ieee_1164_Vector_Is_X, - Iir_Predefined_Ieee_1164_Scalar_Is_X, + Iir_Predefined_Ieee_1164_Is_X_Slv, + Iir_Predefined_Ieee_1164_Is_X_Log, Iir_Predefined_Ieee_1164_Rising_Edge, Iir_Predefined_Ieee_1164_Falling_Edge, @@ -5669,6 +5715,12 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_1164_Condition_Operator, + Iir_Predefined_Ieee_1164_To_01_Log_Log, + Iir_Predefined_Ieee_1164_To_01_Slv_Log, + + Iir_Predefined_Ieee_1164_To_Hstring, + Iir_Predefined_Ieee_1164_To_Ostring, + -- Numeric_Std. -- Abbreviations: -- Uns: Unsigned, Sgn: Signed, Nat: Natural, Int: Integer. @@ -5835,22 +5887,46 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Numeric_Std_Ror_Sgn_Int, Iir_Predefined_Ieee_Numeric_Std_And_Uns_Uns, + Iir_Predefined_Ieee_Numeric_Std_And_Uns_Log, + Iir_Predefined_Ieee_Numeric_Std_And_Log_Uns, Iir_Predefined_Ieee_Numeric_Std_And_Sgn_Sgn, - - Iir_Predefined_Ieee_Numeric_Std_Or_Uns_Uns, - Iir_Predefined_Ieee_Numeric_Std_Or_Sgn_Sgn, + Iir_Predefined_Ieee_Numeric_Std_And_Sgn_Log, + Iir_Predefined_Ieee_Numeric_Std_And_Log_Sgn, Iir_Predefined_Ieee_Numeric_Std_Nand_Uns_Uns, + Iir_Predefined_Ieee_Numeric_Std_Nand_Uns_Log, + Iir_Predefined_Ieee_Numeric_Std_Nand_Log_Uns, Iir_Predefined_Ieee_Numeric_Std_Nand_Sgn_Sgn, + Iir_Predefined_Ieee_Numeric_Std_Nand_Sgn_Log, + Iir_Predefined_Ieee_Numeric_Std_Nand_Log_Sgn, + + Iir_Predefined_Ieee_Numeric_Std_Or_Uns_Uns, + Iir_Predefined_Ieee_Numeric_Std_Or_Uns_Log, + Iir_Predefined_Ieee_Numeric_Std_Or_Log_Uns, + Iir_Predefined_Ieee_Numeric_Std_Or_Sgn_Sgn, + Iir_Predefined_Ieee_Numeric_Std_Or_Sgn_Log, + Iir_Predefined_Ieee_Numeric_Std_Or_Log_Sgn, Iir_Predefined_Ieee_Numeric_Std_Nor_Uns_Uns, + Iir_Predefined_Ieee_Numeric_Std_Nor_Uns_Log, + Iir_Predefined_Ieee_Numeric_Std_Nor_Log_Uns, Iir_Predefined_Ieee_Numeric_Std_Nor_Sgn_Sgn, + Iir_Predefined_Ieee_Numeric_Std_Nor_Sgn_Log, + Iir_Predefined_Ieee_Numeric_Std_Nor_Log_Sgn, Iir_Predefined_Ieee_Numeric_Std_Xor_Uns_Uns, + Iir_Predefined_Ieee_Numeric_Std_Xor_Uns_Log, + Iir_Predefined_Ieee_Numeric_Std_Xor_Log_Uns, Iir_Predefined_Ieee_Numeric_Std_Xor_Sgn_Sgn, + Iir_Predefined_Ieee_Numeric_Std_Xor_Sgn_Log, + Iir_Predefined_Ieee_Numeric_Std_Xor_Log_Sgn, Iir_Predefined_Ieee_Numeric_Std_Xnor_Uns_Uns, + Iir_Predefined_Ieee_Numeric_Std_Xnor_Uns_Log, + Iir_Predefined_Ieee_Numeric_Std_Xnor_Log_Uns, Iir_Predefined_Ieee_Numeric_Std_Xnor_Sgn_Sgn, + Iir_Predefined_Ieee_Numeric_Std_Xnor_Sgn_Log, + Iir_Predefined_Ieee_Numeric_Std_Xnor_Log_Sgn, -- Numeric_Std binary operators (end) -- Unary functions for numeric_std @@ -5918,19 +5994,97 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Numeric_Std_To_01_Uns, Iir_Predefined_Ieee_Numeric_Std_To_01_Sgn, + Iir_Predefined_Ieee_Numeric_Std_To_X01_Uns, + Iir_Predefined_Ieee_Numeric_Std_To_X01_Sgn, + + Iir_Predefined_Ieee_Numeric_Std_To_X01Z_Uns, + Iir_Predefined_Ieee_Numeric_Std_To_X01Z_Sgn, + + Iir_Predefined_Ieee_Numeric_Std_To_UX01_Uns, + Iir_Predefined_Ieee_Numeric_Std_To_UX01_Sgn, + + Iir_Predefined_Ieee_Numeric_Std_Is_X_Uns, + Iir_Predefined_Ieee_Numeric_Std_Is_X_Sgn, + + Iir_Predefined_Ieee_Numeric_Std_To_Hstring_Uns, + Iir_Predefined_Ieee_Numeric_Std_To_Ostring_Uns, + + Iir_Predefined_Ieee_Numeric_Std_To_Hstring_Sgn, + Iir_Predefined_Ieee_Numeric_Std_To_Ostring_Sgn, + + -- numeric_bit + + -- To_Integer, To_Unsigned, to_Signed + Iir_Predefined_Ieee_Numeric_Bit_Toint_Uns_Nat, + Iir_Predefined_Ieee_Numeric_Bit_Toint_Sgn_Int, + Iir_Predefined_Ieee_Numeric_Bit_Touns_Nat_Nat_Uns, + Iir_Predefined_Ieee_Numeric_Bit_Touns_Nat_Uns_Uns, + Iir_Predefined_Ieee_Numeric_Bit_Tosgn_Int_Nat_Sgn, + Iir_Predefined_Ieee_Numeric_Bit_Tosgn_Int_Sgn_Sgn, + -- Numeric_Std_Unsigned (ieee2008) + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Add_Slv_Slv, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Add_Slv_Nat, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Add_Nat_Slv, + + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Sub_Slv_Slv, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Sub_Slv_Nat, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Sub_Nat_Slv, + + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Find_Rightmost, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Find_Leftmost, + + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Shift_Left, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Shift_Right, + + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Rotate_Left, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Rotate_Right, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Integer_Slv_Nat, - Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Nat_Slv, + + Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Nat, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Slv, + + Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Suv_Nat_Nat, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Suv_Nat_Suv, + + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Resize_Slv_Nat, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Resize_Slv_Slv, + + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Maximum_Slv_Slv, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Minimum_Slv_Slv, -- Math_Real + Iir_Predefined_Ieee_Math_Real_Sign, Iir_Predefined_Ieee_Math_Real_Ceil, Iir_Predefined_Ieee_Math_Real_Floor, Iir_Predefined_Ieee_Math_Real_Round, + Iir_Predefined_Ieee_Math_Real_Trunc, + Iir_Predefined_Ieee_Math_Real_Mod, + Iir_Predefined_Ieee_Math_Real_Realmax, + Iir_Predefined_Ieee_Math_Real_Realmin, + Iir_Predefined_Ieee_Math_Real_Sqrt, + Iir_Predefined_Ieee_Math_Real_Cbrt, + Iir_Predefined_Ieee_Math_Real_Pow_Int_Real, + Iir_Predefined_Ieee_Math_Real_Pow_Real_Real, + Iir_Predefined_Ieee_Math_Real_Exp, + Iir_Predefined_Ieee_Math_Real_Log, Iir_Predefined_Ieee_Math_Real_Log2, + Iir_Predefined_Ieee_Math_Real_Log10, + Iir_Predefined_Ieee_Math_Real_Log_Real_Real, Iir_Predefined_Ieee_Math_Real_Sin, Iir_Predefined_Ieee_Math_Real_Cos, + Iir_Predefined_Ieee_Math_Real_Tan, + Iir_Predefined_Ieee_Math_Real_Arcsin, + Iir_Predefined_Ieee_Math_Real_Arccos, Iir_Predefined_Ieee_Math_Real_Arctan, - Iir_Predefined_Ieee_Math_Real_Pow, + Iir_Predefined_Ieee_Math_Real_Arctan_Real_Real, + Iir_Predefined_Ieee_Math_Real_Sinh, + Iir_Predefined_Ieee_Math_Real_Cosh, + Iir_Predefined_Ieee_Math_Real_Tanh, + Iir_Predefined_Ieee_Math_Real_Arcsinh, + Iir_Predefined_Ieee_Math_Real_Arccosh, + Iir_Predefined_Ieee_Math_Real_Arctanh, -- Std_Logic_Unsigned (synopsys extension). Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv, @@ -6199,6 +6353,9 @@ package Vhdl.Nodes is subtype Iir_Predefined_Pure_Functions is Iir_Predefined_Functions range Iir_Predefined_Boolean_And .. Iir_Predefined_Functions'Pred (Iir_Predefined_Deallocate); + subtype Iir_Predefined_Operators is Iir_Predefined_Functions range + Iir_Predefined_Boolean_And .. + Iir_Predefined_Std_Ulogic_Array_Match_Inequality; subtype Iir_Predefined_Impure_Functions is Iir_Predefined_Functions range Iir_Predefined_Deallocate .. Iir_Predefined_Functions'Pred (Iir_Predefined_None); @@ -6265,6 +6422,11 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Numeric_Std_Add_Uns_Uns .. Iir_Predefined_Ieee_Numeric_Std_Xnor_Sgn_Sgn; + subtype Iir_Predefined_Ieee_Numeric_Std_Unsigned_Operators + is Iir_Predefined_Functions range + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Add_Slv_Slv .. + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Sub_Nat_Slv; + -- Size of scalar types. -- Their size is determined during analysis (using the range), so that -- all backends have the same view. @@ -6970,6 +7132,30 @@ package Vhdl.Nodes is --Iir_Kind_Break_Statement Iir_Kind_If_Statement; + -- All sequential statements + suspend_state_statement. + subtype Iir_Kinds_Sequential_Statement_Ext is Iir_Kind range + Iir_Kind_Simple_Signal_Assignment_Statement .. + --Iir_Kind_Conditional_Signal_Assignment_Statement + --Iir_Kind_Selected_Waveform_Assignment_Statement + --Iir_Kind_Signal_Force_Assignment_Statement + --Iir_Kind_Signal_Release_Assignment_Statement + --Iir_Kind_Null_Statement + --Iir_Kind_Assertion_Statement + --Iir_Kind_Report_Statement + --Iir_Kind_Wait_Statement + --Iir_Kind_Variable_Assignment_Statement + --Iir_Kind_Conditional_Variable_Assignment_Statement + --Iir_Kind_Return_Statement + --Iir_Kind_For_Loop_Statement + --Iir_Kind_While_Loop_Statement + --Iir_Kind_Next_Statement + --Iir_Kind_Exit_Statement + --Iir_Kind_Case_Statement + --Iir_Kind_Procedure_Call_Statement + --Iir_Kind_Break_Statement + --Iir_Kind_If_Statement + Iir_Kind_Suspend_State_Statement; + subtype Iir_Kinds_Next_Exit_Statement is Iir_Kind range Iir_Kind_Next_Statement .. Iir_Kind_Exit_Statement; @@ -8908,6 +9094,11 @@ package Vhdl.Nodes is function Get_In_Formal_Flag (Name : Iir) return Boolean; procedure Set_In_Formal_Flag (Name : Iir; Flag : Boolean); + -- True iff the association is an internal association. + -- Field: Flag5 + function Get_Inertial_Flag (Name : Iir) return Boolean; + procedure Set_Inertial_Flag (Name : Iir; Flag : Boolean); + -- The subtype of a slice. Contrary to the Type field, this is not a -- reference. -- Field: Field3 @@ -9326,4 +9517,12 @@ package Vhdl.Nodes is -- Field: Field1 (uc) function Get_Foreign_Node (N : Iir) return Int32; procedure Set_Foreign_Node (N : Iir; En : Int32); + + -- Field: Field3 (uc) + function Get_Suspend_State_Index (N : Iir) return Int32; + procedure Set_Suspend_State_Index (N : Iir; Num : Int32); + + -- Field: Field4 Forward_Ref + function Get_Suspend_State_Chain (N : Iir) return Iir; + procedure Set_Suspend_State_Chain (N : Iir; Chain : Iir); end Vhdl.Nodes; diff --git a/src/vhdl/vhdl-nodes_meta.adb b/src/vhdl/vhdl-nodes_meta.adb index 9fd729275..81b66f3a3 100644 --- a/src/vhdl/vhdl-nodes_meta.adb +++ b/src/vhdl/vhdl-nodes_meta.adb @@ -307,6 +307,7 @@ package body Vhdl.Nodes_Meta is Field_Pathname_Suffix => Type_Iir, Field_Pathname_Expression => Type_Iir, Field_In_Formal_Flag => Type_Boolean, + Field_Inertial_Flag => Type_Boolean, Field_Slice_Subtype => Type_Iir, Field_Suffix => Type_Iir, Field_Index_Subtype => Type_Iir, @@ -389,7 +390,9 @@ package body Vhdl.Nodes_Meta is Field_Count_Expression => Type_Iir, Field_Clock_Expression => Type_Iir, Field_Default_Clock => Type_Iir, - Field_Foreign_Node => Type_Int32 + Field_Foreign_Node => Type_Int32, + Field_Suspend_State_Index => Type_Int32, + Field_Suspend_State_Chain => Type_Iir ); function Get_Field_Type (F : Fields_Enum) return Types_Enum is @@ -980,6 +983,8 @@ package body Vhdl.Nodes_Meta is return "pathname_expression"; when Field_In_Formal_Flag => return "in_formal_flag"; + when Field_Inertial_Flag => + return "inertial_flag"; when Field_Slice_Subtype => return "slice_subtype"; when Field_Suffix => @@ -1146,6 +1151,10 @@ package body Vhdl.Nodes_Meta is return "default_clock"; when Field_Foreign_Node => return "foreign_node"; + when Field_Suspend_State_Index => + return "suspend_state_index"; + when Field_Suspend_State_Chain => + return "suspend_state_chain"; end case; end Get_Field_Image; @@ -1436,6 +1445,8 @@ package body Vhdl.Nodes_Meta is return "interface_procedure_declaration"; when Iir_Kind_Signal_Attribute_Declaration => return "signal_attribute_declaration"; + when Iir_Kind_Suspend_State_Declaration => + return "suspend_state_declaration"; when Iir_Kind_Identity_Operator => return "identity_operator"; when Iir_Kind_Negation_Operator => @@ -1654,6 +1665,8 @@ package body Vhdl.Nodes_Meta is return "break_statement"; when Iir_Kind_If_Statement => return "if_statement"; + when Iir_Kind_Suspend_State_Statement => + return "suspend_state_statement"; when Iir_Kind_Elsif => return "elsif"; when Iir_Kind_Character_Literal => @@ -2378,6 +2391,8 @@ package body Vhdl.Nodes_Meta is return Attr_None; when Field_In_Formal_Flag => return Attr_None; + when Field_Inertial_Flag => + return Attr_None; when Field_Slice_Subtype => return Attr_None; when Field_Suffix => @@ -2544,6 +2559,10 @@ package body Vhdl.Nodes_Meta is return Attr_Ref; when Field_Foreign_Node => return Attr_None; + when Field_Suspend_State_Index => + return Attr_None; + when Field_Suspend_State_Chain => + return Attr_Forward_Ref; end case; end Get_Field_Attribute; @@ -2679,6 +2698,7 @@ package body Vhdl.Nodes_Meta is Field_Whole_Association_Flag, Field_Collapse_Signal_Flag, Field_In_Formal_Flag, + Field_Inertial_Flag, Field_Formal, Field_Chain, Field_Actual, @@ -2827,9 +2847,11 @@ package body Vhdl.Nodes_Meta is Field_Attribute_Specification, Field_Base_Name, -- Iir_Kind_Signature + Field_Is_Forward_Ref, Field_Signature_Prefix, Field_Type_Marks_List, Field_Return_Type_Mark, + Field_Named_Entity, -- Iir_Kind_Aggregate_Info Field_Aggr_Min_Length, Field_Aggr_Others_Flag, @@ -2933,6 +2955,7 @@ package body Vhdl.Nodes_Meta is Field_End_Has_Reserved_Id, Field_End_Has_Identifier, Field_Type_Staticness, + Field_Parent, Field_Declaration_Chain, Field_Protected_Type_Body, Field_Type_Declarator, @@ -3517,9 +3540,7 @@ package body Vhdl.Nodes_Meta is Field_Chain, Field_Interface_Declaration_Chain, Field_Generic_Chain, - Field_Return_Type_Mark, Field_Subprogram_Body, - Field_Return_Identifier, -- Iir_Kind_Function_Body Field_Impure_Depth, Field_End_Has_Reserved_Id, @@ -3922,6 +3943,10 @@ package body Vhdl.Nodes_Meta is Field_Parent, Field_Chain, Field_Signal_Attribute_Chain, + -- Iir_Kind_Suspend_State_Declaration + Field_Parent, + Field_Chain, + Field_Suspend_State_Chain, -- Iir_Kind_Identity_Operator Field_Expr_Staticness, Field_Type, @@ -4776,6 +4801,11 @@ package body Vhdl.Nodes_Meta is Field_Sequential_Statement_Chain, Field_Else_Clause, Field_Chain, + -- Iir_Kind_Suspend_State_Statement + Field_Suspend_State_Index, + Field_Parent, + Field_Chain, + Field_Suspend_State_Chain, -- Iir_Kind_Elsif Field_Is_Ref, Field_End_Has_Identifier, @@ -5282,306 +5312,308 @@ package body Vhdl.Nodes_Meta is Iir_Kind_Waveform_Element => 97, Iir_Kind_Conditional_Waveform => 101, Iir_Kind_Conditional_Expression => 105, - Iir_Kind_Association_Element_By_Expression => 113, - Iir_Kind_Association_Element_By_Name => 121, - Iir_Kind_Association_Element_By_Individual => 130, - Iir_Kind_Association_Element_Open => 136, - Iir_Kind_Association_Element_Package => 142, - Iir_Kind_Association_Element_Type => 150, - Iir_Kind_Association_Element_Subprogram => 156, - Iir_Kind_Association_Element_Terminal => 162, - Iir_Kind_Choice_By_Range => 170, - Iir_Kind_Choice_By_Expression => 178, - Iir_Kind_Choice_By_Others => 184, - Iir_Kind_Choice_By_None => 190, - Iir_Kind_Choice_By_Name => 197, - Iir_Kind_Entity_Aspect_Entity => 199, - Iir_Kind_Entity_Aspect_Configuration => 200, - Iir_Kind_Entity_Aspect_Open => 200, - Iir_Kind_Psl_Hierarchical_Name => 202, - Iir_Kind_Block_Configuration => 208, - Iir_Kind_Block_Header => 212, - Iir_Kind_Component_Configuration => 219, - Iir_Kind_Binding_Indication => 223, - Iir_Kind_Entity_Class => 225, - Iir_Kind_Attribute_Value => 233, - Iir_Kind_Signature => 236, - Iir_Kind_Aggregate_Info => 243, - Iir_Kind_Procedure_Call => 247, - Iir_Kind_Record_Element_Constraint => 255, - Iir_Kind_Array_Element_Resolution => 257, - Iir_Kind_Record_Resolution => 258, - Iir_Kind_Record_Element_Resolution => 261, - Iir_Kind_Break_Element => 265, - Iir_Kind_Attribute_Specification => 274, - Iir_Kind_Disconnection_Specification => 280, - Iir_Kind_Step_Limit_Specification => 286, - Iir_Kind_Configuration_Specification => 292, - Iir_Kind_Access_Type_Definition => 299, - Iir_Kind_Incomplete_Type_Definition => 306, - Iir_Kind_Interface_Type_Definition => 312, - Iir_Kind_File_Type_Definition => 318, - Iir_Kind_Protected_Type_Declaration => 327, - Iir_Kind_Record_Type_Definition => 337, - Iir_Kind_Array_Type_Definition => 348, - Iir_Kind_Array_Subtype_Definition => 365, - Iir_Kind_Record_Subtype_Definition => 378, - Iir_Kind_Access_Subtype_Definition => 386, - Iir_Kind_Physical_Subtype_Definition => 396, - Iir_Kind_Floating_Subtype_Definition => 407, - Iir_Kind_Integer_Subtype_Definition => 417, - Iir_Kind_Enumeration_Subtype_Definition => 427, - Iir_Kind_Enumeration_Type_Definition => 438, - Iir_Kind_Integer_Type_Definition => 446, - Iir_Kind_Floating_Type_Definition => 454, - Iir_Kind_Physical_Type_Definition => 465, - Iir_Kind_Range_Expression => 473, - Iir_Kind_Protected_Type_Body => 481, - Iir_Kind_Wildcard_Type_Definition => 485, - Iir_Kind_Foreign_Vector_Type_Definition => 486, - Iir_Kind_Subtype_Definition => 493, - Iir_Kind_Scalar_Nature_Definition => 501, - Iir_Kind_Record_Nature_Definition => 514, - Iir_Kind_Array_Nature_Definition => 528, - Iir_Kind_Array_Subnature_Definition => 543, - Iir_Kind_Overload_List => 544, - Iir_Kind_Foreign_Module => 549, - Iir_Kind_Entity_Declaration => 562, - Iir_Kind_Configuration_Declaration => 572, - Iir_Kind_Context_Declaration => 578, - Iir_Kind_Package_Declaration => 593, - Iir_Kind_Package_Instantiation_Declaration => 607, - Iir_Kind_Vmode_Declaration => 619, - Iir_Kind_Vprop_Declaration => 631, - Iir_Kind_Vunit_Declaration => 644, - Iir_Kind_Package_Body => 652, - Iir_Kind_Architecture_Body => 665, - Iir_Kind_Type_Declaration => 672, - Iir_Kind_Anonymous_Type_Declaration => 678, - Iir_Kind_Subtype_Declaration => 686, - Iir_Kind_Nature_Declaration => 692, - Iir_Kind_Subnature_Declaration => 699, - Iir_Kind_Package_Header => 701, - Iir_Kind_Unit_Declaration => 710, - Iir_Kind_Library_Declaration => 718, - Iir_Kind_Component_Declaration => 728, - Iir_Kind_Attribute_Declaration => 735, - Iir_Kind_Group_Template_Declaration => 741, - Iir_Kind_Group_Declaration => 748, - Iir_Kind_Element_Declaration => 756, - Iir_Kind_Nature_Element_Declaration => 763, - Iir_Kind_Non_Object_Alias_Declaration => 771, - Iir_Kind_Psl_Declaration => 779, - Iir_Kind_Psl_Endpoint_Declaration => 793, - Iir_Kind_Enumeration_Literal => 805, - Iir_Kind_Function_Declaration => 831, - Iir_Kind_Procedure_Declaration => 856, - Iir_Kind_Function_Body => 866, - Iir_Kind_Procedure_Body => 877, - Iir_Kind_Function_Instantiation_Declaration => 888, - Iir_Kind_Procedure_Instantiation_Declaration => 898, - Iir_Kind_Terminal_Declaration => 907, - Iir_Kind_Object_Alias_Declaration => 919, - Iir_Kind_Free_Quantity_Declaration => 931, - Iir_Kind_Spectrum_Quantity_Declaration => 944, - Iir_Kind_Noise_Quantity_Declaration => 956, - Iir_Kind_Across_Quantity_Declaration => 972, - Iir_Kind_Through_Quantity_Declaration => 988, - Iir_Kind_File_Declaration => 1003, - Iir_Kind_Guard_Signal_Declaration => 1017, - Iir_Kind_Signal_Declaration => 1034, - Iir_Kind_Variable_Declaration => 1047, - Iir_Kind_Constant_Declaration => 1061, - Iir_Kind_Iterator_Declaration => 1073, - Iir_Kind_Interface_Constant_Declaration => 1090, - Iir_Kind_Interface_Variable_Declaration => 1106, - Iir_Kind_Interface_Signal_Declaration => 1127, - Iir_Kind_Interface_File_Declaration => 1143, - Iir_Kind_Interface_Quantity_Declaration => 1159, - Iir_Kind_Interface_Terminal_Declaration => 1171, - Iir_Kind_Interface_Type_Declaration => 1182, - Iir_Kind_Interface_Package_Declaration => 1195, - Iir_Kind_Interface_Function_Declaration => 1213, - Iir_Kind_Interface_Procedure_Declaration => 1227, - Iir_Kind_Signal_Attribute_Declaration => 1230, - Iir_Kind_Identity_Operator => 1234, - Iir_Kind_Negation_Operator => 1238, - Iir_Kind_Absolute_Operator => 1242, - Iir_Kind_Not_Operator => 1246, - Iir_Kind_Implicit_Condition_Operator => 1250, - Iir_Kind_Condition_Operator => 1254, - Iir_Kind_Reduction_And_Operator => 1258, - Iir_Kind_Reduction_Or_Operator => 1262, - Iir_Kind_Reduction_Nand_Operator => 1266, - Iir_Kind_Reduction_Nor_Operator => 1270, - Iir_Kind_Reduction_Xor_Operator => 1274, - Iir_Kind_Reduction_Xnor_Operator => 1278, - Iir_Kind_And_Operator => 1283, - Iir_Kind_Or_Operator => 1288, - Iir_Kind_Nand_Operator => 1293, - Iir_Kind_Nor_Operator => 1298, - Iir_Kind_Xor_Operator => 1303, - Iir_Kind_Xnor_Operator => 1308, - Iir_Kind_Equality_Operator => 1313, - Iir_Kind_Inequality_Operator => 1318, - Iir_Kind_Less_Than_Operator => 1323, - Iir_Kind_Less_Than_Or_Equal_Operator => 1328, - Iir_Kind_Greater_Than_Operator => 1333, - Iir_Kind_Greater_Than_Or_Equal_Operator => 1338, - Iir_Kind_Match_Equality_Operator => 1343, - Iir_Kind_Match_Inequality_Operator => 1348, - Iir_Kind_Match_Less_Than_Operator => 1353, - Iir_Kind_Match_Less_Than_Or_Equal_Operator => 1358, - Iir_Kind_Match_Greater_Than_Operator => 1363, - Iir_Kind_Match_Greater_Than_Or_Equal_Operator => 1368, - Iir_Kind_Sll_Operator => 1373, - Iir_Kind_Sla_Operator => 1378, - Iir_Kind_Srl_Operator => 1383, - Iir_Kind_Sra_Operator => 1388, - Iir_Kind_Rol_Operator => 1393, - Iir_Kind_Ror_Operator => 1398, - Iir_Kind_Addition_Operator => 1403, - Iir_Kind_Substraction_Operator => 1408, - Iir_Kind_Concatenation_Operator => 1413, - Iir_Kind_Multiplication_Operator => 1418, - Iir_Kind_Division_Operator => 1423, - Iir_Kind_Modulus_Operator => 1428, - Iir_Kind_Remainder_Operator => 1433, - Iir_Kind_Exponentiation_Operator => 1438, - Iir_Kind_Function_Call => 1446, - Iir_Kind_Aggregate => 1453, - Iir_Kind_Parenthesis_Expression => 1456, - Iir_Kind_Qualified_Expression => 1460, - Iir_Kind_Type_Conversion => 1465, - Iir_Kind_Allocator_By_Expression => 1470, - Iir_Kind_Allocator_By_Subtype => 1476, - Iir_Kind_Selected_Element => 1484, - Iir_Kind_Dereference => 1489, - Iir_Kind_Implicit_Dereference => 1494, - Iir_Kind_Slice_Name => 1501, - Iir_Kind_Indexed_Name => 1507, - Iir_Kind_Psl_Prev => 1513, - Iir_Kind_Psl_Stable => 1518, - Iir_Kind_Psl_Rose => 1523, - Iir_Kind_Psl_Fell => 1528, - Iir_Kind_Psl_Onehot => 1531, - Iir_Kind_Psl_Onehot0 => 1534, - Iir_Kind_Psl_Expression => 1536, - Iir_Kind_Sensitized_Process_Statement => 1557, - Iir_Kind_Process_Statement => 1577, - Iir_Kind_Concurrent_Simple_Signal_Assignment => 1590, - Iir_Kind_Concurrent_Conditional_Signal_Assignment => 1603, - Iir_Kind_Concurrent_Selected_Signal_Assignment => 1617, - Iir_Kind_Concurrent_Assertion_Statement => 1625, - Iir_Kind_Concurrent_Procedure_Call_Statement => 1632, - Iir_Kind_Concurrent_Break_Statement => 1640, - Iir_Kind_Psl_Assert_Directive => 1654, - Iir_Kind_Psl_Assume_Directive => 1666, - Iir_Kind_Psl_Cover_Directive => 1678, - Iir_Kind_Psl_Restrict_Directive => 1689, - Iir_Kind_Block_Statement => 1703, - Iir_Kind_If_Generate_Statement => 1714, - Iir_Kind_Case_Generate_Statement => 1723, - Iir_Kind_For_Generate_Statement => 1732, - Iir_Kind_Component_Instantiation_Statement => 1743, - Iir_Kind_Psl_Default_Clock => 1746, - Iir_Kind_Generate_Statement_Body => 1757, - Iir_Kind_If_Generate_Else_Clause => 1763, - Iir_Kind_Simple_Simultaneous_Statement => 1770, - Iir_Kind_Simultaneous_Null_Statement => 1774, - Iir_Kind_Simultaneous_Procedural_Statement => 1785, - Iir_Kind_Simultaneous_Case_Statement => 1794, - Iir_Kind_Simultaneous_If_Statement => 1803, - Iir_Kind_Simultaneous_Elsif => 1809, - Iir_Kind_Simple_Signal_Assignment_Statement => 1820, - Iir_Kind_Conditional_Signal_Assignment_Statement => 1831, - Iir_Kind_Selected_Waveform_Assignment_Statement => 1843, - Iir_Kind_Signal_Force_Assignment_Statement => 1853, - Iir_Kind_Signal_Release_Assignment_Statement => 1862, - Iir_Kind_Null_Statement => 1866, - Iir_Kind_Assertion_Statement => 1873, - Iir_Kind_Report_Statement => 1879, - Iir_Kind_Wait_Statement => 1887, - Iir_Kind_Variable_Assignment_Statement => 1894, - Iir_Kind_Conditional_Variable_Assignment_Statement => 1901, - Iir_Kind_Return_Statement => 1907, - Iir_Kind_For_Loop_Statement => 1918, - Iir_Kind_While_Loop_Statement => 1929, - Iir_Kind_Next_Statement => 1936, - Iir_Kind_Exit_Statement => 1943, - Iir_Kind_Case_Statement => 1952, - Iir_Kind_Procedure_Call_Statement => 1958, - Iir_Kind_Break_Statement => 1965, - Iir_Kind_If_Statement => 1975, - Iir_Kind_Elsif => 1981, - Iir_Kind_Character_Literal => 1988, - Iir_Kind_Simple_Name => 1995, - Iir_Kind_Selected_Name => 2003, - Iir_Kind_Operator_Symbol => 2008, - Iir_Kind_Reference_Name => 2013, - Iir_Kind_External_Constant_Name => 2022, - Iir_Kind_External_Signal_Name => 2031, - Iir_Kind_External_Variable_Name => 2041, - Iir_Kind_Selected_By_All_Name => 2047, - Iir_Kind_Parenthesis_Name => 2052, - Iir_Kind_Package_Pathname => 2056, - Iir_Kind_Absolute_Pathname => 2057, - Iir_Kind_Relative_Pathname => 2058, - Iir_Kind_Pathname_Element => 2063, - Iir_Kind_Base_Attribute => 2065, - Iir_Kind_Subtype_Attribute => 2070, - Iir_Kind_Element_Attribute => 2075, - Iir_Kind_Across_Attribute => 2080, - Iir_Kind_Through_Attribute => 2085, - Iir_Kind_Nature_Reference_Attribute => 2089, - Iir_Kind_Left_Type_Attribute => 2094, - Iir_Kind_Right_Type_Attribute => 2099, - Iir_Kind_High_Type_Attribute => 2104, - Iir_Kind_Low_Type_Attribute => 2109, - Iir_Kind_Ascending_Type_Attribute => 2114, - Iir_Kind_Image_Attribute => 2120, - Iir_Kind_Value_Attribute => 2126, - Iir_Kind_Pos_Attribute => 2132, - Iir_Kind_Val_Attribute => 2138, - Iir_Kind_Succ_Attribute => 2144, - Iir_Kind_Pred_Attribute => 2150, - Iir_Kind_Leftof_Attribute => 2156, - Iir_Kind_Rightof_Attribute => 2162, - Iir_Kind_Signal_Slew_Attribute => 2170, - Iir_Kind_Quantity_Slew_Attribute => 2178, - Iir_Kind_Ramp_Attribute => 2186, - Iir_Kind_Zoh_Attribute => 2194, - Iir_Kind_Ltf_Attribute => 2202, - Iir_Kind_Ztf_Attribute => 2212, - Iir_Kind_Dot_Attribute => 2219, - Iir_Kind_Integ_Attribute => 2226, - Iir_Kind_Above_Attribute => 2234, - Iir_Kind_Quantity_Delayed_Attribute => 2242, - Iir_Kind_Delayed_Attribute => 2251, - Iir_Kind_Stable_Attribute => 2260, - Iir_Kind_Quiet_Attribute => 2269, - Iir_Kind_Transaction_Attribute => 2278, - Iir_Kind_Event_Attribute => 2282, - Iir_Kind_Active_Attribute => 2286, - Iir_Kind_Last_Event_Attribute => 2290, - Iir_Kind_Last_Active_Attribute => 2294, - Iir_Kind_Last_Value_Attribute => 2298, - Iir_Kind_Driving_Attribute => 2302, - Iir_Kind_Driving_Value_Attribute => 2306, - Iir_Kind_Behavior_Attribute => 2306, - Iir_Kind_Structure_Attribute => 2306, - Iir_Kind_Simple_Name_Attribute => 2313, - Iir_Kind_Instance_Name_Attribute => 2318, - Iir_Kind_Path_Name_Attribute => 2323, - Iir_Kind_Left_Array_Attribute => 2330, - Iir_Kind_Right_Array_Attribute => 2337, - Iir_Kind_High_Array_Attribute => 2344, - Iir_Kind_Low_Array_Attribute => 2351, - Iir_Kind_Length_Array_Attribute => 2358, - Iir_Kind_Ascending_Array_Attribute => 2365, - Iir_Kind_Range_Array_Attribute => 2372, - Iir_Kind_Reverse_Range_Array_Attribute => 2379, - Iir_Kind_Attribute_Name => 2388 + Iir_Kind_Association_Element_By_Expression => 114, + Iir_Kind_Association_Element_By_Name => 122, + Iir_Kind_Association_Element_By_Individual => 131, + Iir_Kind_Association_Element_Open => 137, + Iir_Kind_Association_Element_Package => 143, + Iir_Kind_Association_Element_Type => 151, + Iir_Kind_Association_Element_Subprogram => 157, + Iir_Kind_Association_Element_Terminal => 163, + Iir_Kind_Choice_By_Range => 171, + Iir_Kind_Choice_By_Expression => 179, + Iir_Kind_Choice_By_Others => 185, + Iir_Kind_Choice_By_None => 191, + Iir_Kind_Choice_By_Name => 198, + Iir_Kind_Entity_Aspect_Entity => 200, + Iir_Kind_Entity_Aspect_Configuration => 201, + Iir_Kind_Entity_Aspect_Open => 201, + Iir_Kind_Psl_Hierarchical_Name => 203, + Iir_Kind_Block_Configuration => 209, + Iir_Kind_Block_Header => 213, + Iir_Kind_Component_Configuration => 220, + Iir_Kind_Binding_Indication => 224, + Iir_Kind_Entity_Class => 226, + Iir_Kind_Attribute_Value => 234, + Iir_Kind_Signature => 239, + Iir_Kind_Aggregate_Info => 246, + Iir_Kind_Procedure_Call => 250, + Iir_Kind_Record_Element_Constraint => 258, + Iir_Kind_Array_Element_Resolution => 260, + Iir_Kind_Record_Resolution => 261, + Iir_Kind_Record_Element_Resolution => 264, + Iir_Kind_Break_Element => 268, + Iir_Kind_Attribute_Specification => 277, + Iir_Kind_Disconnection_Specification => 283, + Iir_Kind_Step_Limit_Specification => 289, + Iir_Kind_Configuration_Specification => 295, + Iir_Kind_Access_Type_Definition => 302, + Iir_Kind_Incomplete_Type_Definition => 309, + Iir_Kind_Interface_Type_Definition => 315, + Iir_Kind_File_Type_Definition => 321, + Iir_Kind_Protected_Type_Declaration => 331, + Iir_Kind_Record_Type_Definition => 341, + Iir_Kind_Array_Type_Definition => 352, + Iir_Kind_Array_Subtype_Definition => 369, + Iir_Kind_Record_Subtype_Definition => 382, + Iir_Kind_Access_Subtype_Definition => 390, + Iir_Kind_Physical_Subtype_Definition => 400, + Iir_Kind_Floating_Subtype_Definition => 411, + Iir_Kind_Integer_Subtype_Definition => 421, + Iir_Kind_Enumeration_Subtype_Definition => 431, + Iir_Kind_Enumeration_Type_Definition => 442, + Iir_Kind_Integer_Type_Definition => 450, + Iir_Kind_Floating_Type_Definition => 458, + Iir_Kind_Physical_Type_Definition => 469, + Iir_Kind_Range_Expression => 477, + Iir_Kind_Protected_Type_Body => 485, + Iir_Kind_Wildcard_Type_Definition => 489, + Iir_Kind_Foreign_Vector_Type_Definition => 490, + Iir_Kind_Subtype_Definition => 497, + Iir_Kind_Scalar_Nature_Definition => 505, + Iir_Kind_Record_Nature_Definition => 518, + Iir_Kind_Array_Nature_Definition => 532, + Iir_Kind_Array_Subnature_Definition => 547, + Iir_Kind_Overload_List => 548, + Iir_Kind_Foreign_Module => 553, + Iir_Kind_Entity_Declaration => 566, + Iir_Kind_Configuration_Declaration => 576, + Iir_Kind_Context_Declaration => 582, + Iir_Kind_Package_Declaration => 597, + Iir_Kind_Package_Instantiation_Declaration => 611, + Iir_Kind_Vmode_Declaration => 623, + Iir_Kind_Vprop_Declaration => 635, + Iir_Kind_Vunit_Declaration => 648, + Iir_Kind_Package_Body => 656, + Iir_Kind_Architecture_Body => 669, + Iir_Kind_Type_Declaration => 676, + Iir_Kind_Anonymous_Type_Declaration => 682, + Iir_Kind_Subtype_Declaration => 690, + Iir_Kind_Nature_Declaration => 696, + Iir_Kind_Subnature_Declaration => 703, + Iir_Kind_Package_Header => 705, + Iir_Kind_Unit_Declaration => 714, + Iir_Kind_Library_Declaration => 722, + Iir_Kind_Component_Declaration => 732, + Iir_Kind_Attribute_Declaration => 739, + Iir_Kind_Group_Template_Declaration => 745, + Iir_Kind_Group_Declaration => 752, + Iir_Kind_Element_Declaration => 760, + Iir_Kind_Nature_Element_Declaration => 767, + Iir_Kind_Non_Object_Alias_Declaration => 775, + Iir_Kind_Psl_Declaration => 783, + Iir_Kind_Psl_Endpoint_Declaration => 797, + Iir_Kind_Enumeration_Literal => 809, + Iir_Kind_Function_Declaration => 835, + Iir_Kind_Procedure_Declaration => 858, + Iir_Kind_Function_Body => 868, + Iir_Kind_Procedure_Body => 879, + Iir_Kind_Function_Instantiation_Declaration => 890, + Iir_Kind_Procedure_Instantiation_Declaration => 900, + Iir_Kind_Terminal_Declaration => 909, + Iir_Kind_Object_Alias_Declaration => 921, + Iir_Kind_Free_Quantity_Declaration => 933, + Iir_Kind_Spectrum_Quantity_Declaration => 946, + Iir_Kind_Noise_Quantity_Declaration => 958, + Iir_Kind_Across_Quantity_Declaration => 974, + Iir_Kind_Through_Quantity_Declaration => 990, + Iir_Kind_File_Declaration => 1005, + Iir_Kind_Guard_Signal_Declaration => 1019, + Iir_Kind_Signal_Declaration => 1036, + Iir_Kind_Variable_Declaration => 1049, + Iir_Kind_Constant_Declaration => 1063, + Iir_Kind_Iterator_Declaration => 1075, + Iir_Kind_Interface_Constant_Declaration => 1092, + Iir_Kind_Interface_Variable_Declaration => 1108, + Iir_Kind_Interface_Signal_Declaration => 1129, + Iir_Kind_Interface_File_Declaration => 1145, + Iir_Kind_Interface_Quantity_Declaration => 1161, + Iir_Kind_Interface_Terminal_Declaration => 1173, + Iir_Kind_Interface_Type_Declaration => 1184, + Iir_Kind_Interface_Package_Declaration => 1197, + Iir_Kind_Interface_Function_Declaration => 1215, + Iir_Kind_Interface_Procedure_Declaration => 1229, + Iir_Kind_Signal_Attribute_Declaration => 1232, + Iir_Kind_Suspend_State_Declaration => 1235, + Iir_Kind_Identity_Operator => 1239, + Iir_Kind_Negation_Operator => 1243, + Iir_Kind_Absolute_Operator => 1247, + Iir_Kind_Not_Operator => 1251, + Iir_Kind_Implicit_Condition_Operator => 1255, + Iir_Kind_Condition_Operator => 1259, + Iir_Kind_Reduction_And_Operator => 1263, + Iir_Kind_Reduction_Or_Operator => 1267, + Iir_Kind_Reduction_Nand_Operator => 1271, + Iir_Kind_Reduction_Nor_Operator => 1275, + Iir_Kind_Reduction_Xor_Operator => 1279, + Iir_Kind_Reduction_Xnor_Operator => 1283, + Iir_Kind_And_Operator => 1288, + Iir_Kind_Or_Operator => 1293, + Iir_Kind_Nand_Operator => 1298, + Iir_Kind_Nor_Operator => 1303, + Iir_Kind_Xor_Operator => 1308, + Iir_Kind_Xnor_Operator => 1313, + Iir_Kind_Equality_Operator => 1318, + Iir_Kind_Inequality_Operator => 1323, + Iir_Kind_Less_Than_Operator => 1328, + Iir_Kind_Less_Than_Or_Equal_Operator => 1333, + Iir_Kind_Greater_Than_Operator => 1338, + Iir_Kind_Greater_Than_Or_Equal_Operator => 1343, + Iir_Kind_Match_Equality_Operator => 1348, + Iir_Kind_Match_Inequality_Operator => 1353, + Iir_Kind_Match_Less_Than_Operator => 1358, + Iir_Kind_Match_Less_Than_Or_Equal_Operator => 1363, + Iir_Kind_Match_Greater_Than_Operator => 1368, + Iir_Kind_Match_Greater_Than_Or_Equal_Operator => 1373, + Iir_Kind_Sll_Operator => 1378, + Iir_Kind_Sla_Operator => 1383, + Iir_Kind_Srl_Operator => 1388, + Iir_Kind_Sra_Operator => 1393, + Iir_Kind_Rol_Operator => 1398, + Iir_Kind_Ror_Operator => 1403, + Iir_Kind_Addition_Operator => 1408, + Iir_Kind_Substraction_Operator => 1413, + Iir_Kind_Concatenation_Operator => 1418, + Iir_Kind_Multiplication_Operator => 1423, + Iir_Kind_Division_Operator => 1428, + Iir_Kind_Modulus_Operator => 1433, + Iir_Kind_Remainder_Operator => 1438, + Iir_Kind_Exponentiation_Operator => 1443, + Iir_Kind_Function_Call => 1451, + Iir_Kind_Aggregate => 1458, + Iir_Kind_Parenthesis_Expression => 1461, + Iir_Kind_Qualified_Expression => 1465, + Iir_Kind_Type_Conversion => 1470, + Iir_Kind_Allocator_By_Expression => 1475, + Iir_Kind_Allocator_By_Subtype => 1481, + Iir_Kind_Selected_Element => 1489, + Iir_Kind_Dereference => 1494, + Iir_Kind_Implicit_Dereference => 1499, + Iir_Kind_Slice_Name => 1506, + Iir_Kind_Indexed_Name => 1512, + Iir_Kind_Psl_Prev => 1518, + Iir_Kind_Psl_Stable => 1523, + Iir_Kind_Psl_Rose => 1528, + Iir_Kind_Psl_Fell => 1533, + Iir_Kind_Psl_Onehot => 1536, + Iir_Kind_Psl_Onehot0 => 1539, + Iir_Kind_Psl_Expression => 1541, + Iir_Kind_Sensitized_Process_Statement => 1562, + Iir_Kind_Process_Statement => 1582, + Iir_Kind_Concurrent_Simple_Signal_Assignment => 1595, + Iir_Kind_Concurrent_Conditional_Signal_Assignment => 1608, + Iir_Kind_Concurrent_Selected_Signal_Assignment => 1622, + Iir_Kind_Concurrent_Assertion_Statement => 1630, + Iir_Kind_Concurrent_Procedure_Call_Statement => 1637, + Iir_Kind_Concurrent_Break_Statement => 1645, + Iir_Kind_Psl_Assert_Directive => 1659, + Iir_Kind_Psl_Assume_Directive => 1671, + Iir_Kind_Psl_Cover_Directive => 1683, + Iir_Kind_Psl_Restrict_Directive => 1694, + Iir_Kind_Block_Statement => 1708, + Iir_Kind_If_Generate_Statement => 1719, + Iir_Kind_Case_Generate_Statement => 1728, + Iir_Kind_For_Generate_Statement => 1737, + Iir_Kind_Component_Instantiation_Statement => 1748, + Iir_Kind_Psl_Default_Clock => 1751, + Iir_Kind_Generate_Statement_Body => 1762, + Iir_Kind_If_Generate_Else_Clause => 1768, + Iir_Kind_Simple_Simultaneous_Statement => 1775, + Iir_Kind_Simultaneous_Null_Statement => 1779, + Iir_Kind_Simultaneous_Procedural_Statement => 1790, + Iir_Kind_Simultaneous_Case_Statement => 1799, + Iir_Kind_Simultaneous_If_Statement => 1808, + Iir_Kind_Simultaneous_Elsif => 1814, + Iir_Kind_Simple_Signal_Assignment_Statement => 1825, + Iir_Kind_Conditional_Signal_Assignment_Statement => 1836, + Iir_Kind_Selected_Waveform_Assignment_Statement => 1848, + Iir_Kind_Signal_Force_Assignment_Statement => 1858, + Iir_Kind_Signal_Release_Assignment_Statement => 1867, + Iir_Kind_Null_Statement => 1871, + Iir_Kind_Assertion_Statement => 1878, + Iir_Kind_Report_Statement => 1884, + Iir_Kind_Wait_Statement => 1892, + Iir_Kind_Variable_Assignment_Statement => 1899, + Iir_Kind_Conditional_Variable_Assignment_Statement => 1906, + Iir_Kind_Return_Statement => 1912, + Iir_Kind_For_Loop_Statement => 1923, + Iir_Kind_While_Loop_Statement => 1934, + Iir_Kind_Next_Statement => 1941, + Iir_Kind_Exit_Statement => 1948, + Iir_Kind_Case_Statement => 1957, + Iir_Kind_Procedure_Call_Statement => 1963, + Iir_Kind_Break_Statement => 1970, + Iir_Kind_If_Statement => 1980, + Iir_Kind_Suspend_State_Statement => 1984, + Iir_Kind_Elsif => 1990, + Iir_Kind_Character_Literal => 1997, + Iir_Kind_Simple_Name => 2004, + Iir_Kind_Selected_Name => 2012, + Iir_Kind_Operator_Symbol => 2017, + Iir_Kind_Reference_Name => 2022, + Iir_Kind_External_Constant_Name => 2031, + Iir_Kind_External_Signal_Name => 2040, + Iir_Kind_External_Variable_Name => 2050, + Iir_Kind_Selected_By_All_Name => 2056, + Iir_Kind_Parenthesis_Name => 2061, + Iir_Kind_Package_Pathname => 2065, + Iir_Kind_Absolute_Pathname => 2066, + Iir_Kind_Relative_Pathname => 2067, + Iir_Kind_Pathname_Element => 2072, + Iir_Kind_Base_Attribute => 2074, + Iir_Kind_Subtype_Attribute => 2079, + Iir_Kind_Element_Attribute => 2084, + Iir_Kind_Across_Attribute => 2089, + Iir_Kind_Through_Attribute => 2094, + Iir_Kind_Nature_Reference_Attribute => 2098, + Iir_Kind_Left_Type_Attribute => 2103, + Iir_Kind_Right_Type_Attribute => 2108, + Iir_Kind_High_Type_Attribute => 2113, + Iir_Kind_Low_Type_Attribute => 2118, + Iir_Kind_Ascending_Type_Attribute => 2123, + Iir_Kind_Image_Attribute => 2129, + Iir_Kind_Value_Attribute => 2135, + Iir_Kind_Pos_Attribute => 2141, + Iir_Kind_Val_Attribute => 2147, + Iir_Kind_Succ_Attribute => 2153, + Iir_Kind_Pred_Attribute => 2159, + Iir_Kind_Leftof_Attribute => 2165, + Iir_Kind_Rightof_Attribute => 2171, + Iir_Kind_Signal_Slew_Attribute => 2179, + Iir_Kind_Quantity_Slew_Attribute => 2187, + Iir_Kind_Ramp_Attribute => 2195, + Iir_Kind_Zoh_Attribute => 2203, + Iir_Kind_Ltf_Attribute => 2211, + Iir_Kind_Ztf_Attribute => 2221, + Iir_Kind_Dot_Attribute => 2228, + Iir_Kind_Integ_Attribute => 2235, + Iir_Kind_Above_Attribute => 2243, + Iir_Kind_Quantity_Delayed_Attribute => 2251, + Iir_Kind_Delayed_Attribute => 2260, + Iir_Kind_Stable_Attribute => 2269, + Iir_Kind_Quiet_Attribute => 2278, + Iir_Kind_Transaction_Attribute => 2287, + Iir_Kind_Event_Attribute => 2291, + Iir_Kind_Active_Attribute => 2295, + Iir_Kind_Last_Event_Attribute => 2299, + Iir_Kind_Last_Active_Attribute => 2303, + Iir_Kind_Last_Value_Attribute => 2307, + Iir_Kind_Driving_Attribute => 2311, + Iir_Kind_Driving_Value_Attribute => 2315, + Iir_Kind_Behavior_Attribute => 2315, + Iir_Kind_Structure_Attribute => 2315, + Iir_Kind_Simple_Name_Attribute => 2322, + Iir_Kind_Instance_Name_Attribute => 2327, + Iir_Kind_Path_Name_Attribute => 2332, + Iir_Kind_Left_Array_Attribute => 2339, + Iir_Kind_Right_Array_Attribute => 2346, + Iir_Kind_High_Array_Attribute => 2353, + Iir_Kind_Low_Array_Attribute => 2360, + Iir_Kind_Length_Array_Attribute => 2367, + Iir_Kind_Ascending_Array_Attribute => 2374, + Iir_Kind_Range_Array_Attribute => 2381, + Iir_Kind_Reverse_Range_Array_Attribute => 2388, + Iir_Kind_Attribute_Name => 2397 ); function Get_Fields_First (K : Iir_Kind) return Fields_Index is @@ -5700,6 +5732,8 @@ package body Vhdl.Nodes_Meta is return Get_Next_Flag (N); when Field_In_Formal_Flag => return Get_In_Formal_Flag (N); + when Field_Inertial_Flag => + return Get_Inertial_Flag (N); when Field_Aggr_Dynamic_Flag => return Get_Aggr_Dynamic_Flag (N); when Field_Aggr_Others_Flag => @@ -5854,6 +5888,8 @@ package body Vhdl.Nodes_Meta is Set_Next_Flag (N, V); when Field_In_Formal_Flag => Set_In_Formal_Flag (N, V); + when Field_Inertial_Flag => + Set_Inertial_Flag (N, V); when Field_Aggr_Dynamic_Flag => Set_Aggr_Dynamic_Flag (N, V); when Field_Aggr_Others_Flag => @@ -6492,6 +6528,8 @@ package body Vhdl.Nodes_Meta is return Get_Clock_Expression (N); when Field_Default_Clock => return Get_Default_Clock (N); + when Field_Suspend_State_Chain => + return Get_Suspend_State_Chain (N); when others => raise Internal_Error; end case; @@ -6950,6 +6988,8 @@ package body Vhdl.Nodes_Meta is Set_Clock_Expression (N, V); when Field_Default_Clock => Set_Default_Clock (N, V); + when Field_Suspend_State_Chain => + Set_Suspend_State_Chain (N, V); when others => raise Internal_Error; end case; @@ -7396,6 +7436,8 @@ package body Vhdl.Nodes_Meta is return Get_PSL_Nbr_States (N); when Field_Foreign_Node => return Get_Foreign_Node (N); + when Field_Suspend_State_Index => + return Get_Suspend_State_Index (N); when others => raise Internal_Error; end case; @@ -7418,6 +7460,8 @@ package body Vhdl.Nodes_Meta is Set_PSL_Nbr_States (N, V); when Field_Foreign_Node => Set_Foreign_Node (N, V); + when Field_Suspend_State_Index => + Set_Suspend_State_Index (N, V); when others => raise Internal_Error; end case; @@ -8570,6 +8614,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_Function_Declaration | Iir_Kind_Interface_Procedure_Declaration | Iir_Kind_Signal_Attribute_Declaration + | Iir_Kind_Suspend_State_Declaration | Iir_Kind_Sensitized_Process_Statement | Iir_Kind_Process_Statement | Iir_Kind_Concurrent_Simple_Signal_Assignment @@ -8613,6 +8658,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Procedure_Call_Statement | Iir_Kind_Break_Statement | Iir_Kind_If_Statement + | Iir_Kind_Suspend_State_Statement | Iir_Kind_External_Constant_Name | Iir_Kind_External_Signal_Name | Iir_Kind_External_Variable_Name => @@ -9583,13 +9629,7 @@ package body Vhdl.Nodes_Meta is function Has_Return_Identifier (K : Iir_Kind) return Boolean is begin - case K is - when Iir_Kind_Function_Declaration - | Iir_Kind_Procedure_Declaration => - return True; - when others => - return False; - end case; + return K = Iir_Kind_Function_Declaration; end Has_Return_Identifier; function Has_Visible_Flag (K : Iir_Kind) return Boolean is @@ -10939,6 +10979,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Disconnection_Specification | Iir_Kind_Step_Limit_Specification | Iir_Kind_Configuration_Specification + | Iir_Kind_Protected_Type_Declaration | Iir_Kind_Protected_Type_Body | Iir_Kind_Foreign_Module | Iir_Kind_Entity_Declaration @@ -10997,6 +11038,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Interface_Function_Declaration | Iir_Kind_Interface_Procedure_Declaration | Iir_Kind_Signal_Attribute_Declaration + | Iir_Kind_Suspend_State_Declaration | Iir_Kind_Sensitized_Process_Statement | Iir_Kind_Process_Statement | Iir_Kind_Concurrent_Simple_Signal_Assignment @@ -11043,6 +11085,7 @@ package body Vhdl.Nodes_Meta is | Iir_Kind_Procedure_Call_Statement | Iir_Kind_Break_Statement | Iir_Kind_If_Statement + | Iir_Kind_Suspend_State_Statement | Iir_Kind_Elsif | Iir_Kind_External_Constant_Name | Iir_Kind_External_Signal_Name @@ -11132,7 +11175,8 @@ package body Vhdl.Nodes_Meta is function Has_Named_Entity (K : Iir_Kind) return Boolean is begin case K is - when Iir_Kind_Selected_Element + when Iir_Kind_Signature + | Iir_Kind_Selected_Element | Iir_Kind_Character_Literal | Iir_Kind_Simple_Name | Iir_Kind_Selected_Name @@ -11693,6 +11737,11 @@ package body Vhdl.Nodes_Meta is end case; end Has_In_Formal_Flag; + function Has_Inertial_Flag (K : Iir_Kind) return Boolean is + begin + return K = Iir_Kind_Association_Element_By_Expression; + end Has_Inertial_Flag; + function Has_Slice_Subtype (K : Iir_Kind) return Boolean is begin return K = Iir_Kind_Slice_Name; @@ -12072,7 +12121,6 @@ package body Vhdl.Nodes_Meta is case K is when Iir_Kind_Signature | Iir_Kind_Function_Declaration - | Iir_Kind_Procedure_Declaration | Iir_Kind_Interface_Function_Declaration | Iir_Kind_Interface_Procedure_Declaration => return True; @@ -12577,7 +12625,8 @@ package body Vhdl.Nodes_Meta is function Has_Is_Forward_Ref (K : Iir_Kind) return Boolean is begin case K is - when Iir_Kind_Selected_Element + when Iir_Kind_Signature + | Iir_Kind_Selected_Element | Iir_Kind_Character_Literal | Iir_Kind_Simple_Name | Iir_Kind_Selected_Name @@ -12756,4 +12805,20 @@ package body Vhdl.Nodes_Meta is return K = Iir_Kind_Foreign_Module; end Has_Foreign_Node; + function Has_Suspend_State_Index (K : Iir_Kind) return Boolean is + begin + return K = Iir_Kind_Suspend_State_Statement; + end Has_Suspend_State_Index; + + function Has_Suspend_State_Chain (K : Iir_Kind) return Boolean is + begin + case K is + when Iir_Kind_Suspend_State_Declaration + | Iir_Kind_Suspend_State_Statement => + return True; + when others => + return False; + end case; + end Has_Suspend_State_Chain; + end Vhdl.Nodes_Meta; diff --git a/src/vhdl/vhdl-nodes_meta.ads b/src/vhdl/vhdl-nodes_meta.ads index 15e9c1b3d..bf7fdcae0 100644 --- a/src/vhdl/vhdl-nodes_meta.ads +++ b/src/vhdl/vhdl-nodes_meta.ads @@ -351,6 +351,7 @@ package Vhdl.Nodes_Meta is Field_Pathname_Suffix, Field_Pathname_Expression, Field_In_Formal_Flag, + Field_Inertial_Flag, Field_Slice_Subtype, Field_Suffix, Field_Index_Subtype, @@ -433,7 +434,9 @@ package Vhdl.Nodes_Meta is Field_Count_Expression, Field_Clock_Expression, Field_Default_Clock, - Field_Foreign_Node + Field_Foreign_Node, + Field_Suspend_State_Index, + Field_Suspend_State_Chain ); pragma Discard_Names (Fields_Enum); @@ -942,6 +945,7 @@ package Vhdl.Nodes_Meta is function Has_Pathname_Suffix (K : Iir_Kind) return Boolean; function Has_Pathname_Expression (K : Iir_Kind) return Boolean; function Has_In_Formal_Flag (K : Iir_Kind) return Boolean; + function Has_Inertial_Flag (K : Iir_Kind) return Boolean; function Has_Slice_Subtype (K : Iir_Kind) return Boolean; function Has_Suffix (K : Iir_Kind) return Boolean; function Has_Index_Subtype (K : Iir_Kind) return Boolean; @@ -1026,4 +1030,6 @@ package Vhdl.Nodes_Meta is function Has_Clock_Expression (K : Iir_Kind) return Boolean; function Has_Default_Clock (K : Iir_Kind) return Boolean; function Has_Foreign_Node (K : Iir_Kind) return Boolean; + function Has_Suspend_State_Index (K : Iir_Kind) return Boolean; + function Has_Suspend_State_Chain (K : Iir_Kind) return Boolean; end Vhdl.Nodes_Meta; diff --git a/src/vhdl/vhdl-nodes_walk.adb b/src/vhdl/vhdl-nodes_walk.adb index fdd6d0c5d..442c105b7 100644 --- a/src/vhdl/vhdl-nodes_walk.adb +++ b/src/vhdl/vhdl-nodes_walk.adb @@ -57,7 +57,7 @@ package body Vhdl.Nodes_Walk is Status : Walk_Status := Walk_Continue; Chain : Iir; begin - case Iir_Kinds_Sequential_Statement (Get_Kind (Stmt)) is + case Iir_Kinds_Sequential_Statement_Ext (Get_Kind (Stmt)) is when Iir_Kind_Simple_Signal_Assignment_Statement | Iir_Kind_Conditional_Signal_Assignment_Statement | Iir_Kind_Selected_Waveform_Assignment_Statement @@ -73,7 +73,8 @@ package body Vhdl.Nodes_Walk is | Iir_Kind_Exit_Statement | Iir_Kind_Variable_Assignment_Statement | Iir_Kind_Conditional_Variable_Assignment_Statement - | Iir_Kind_Break_Statement => + | Iir_Kind_Break_Statement + | Iir_Kind_Suspend_State_Statement => null; when Iir_Kind_For_Loop_Statement | Iir_Kind_While_Loop_Statement => diff --git a/src/vhdl/vhdl-parse.adb b/src/vhdl/vhdl-parse.adb index 6e574b0a5..60dfd103c 100644 --- a/src/vhdl/vhdl-parse.adb +++ b/src/vhdl/vhdl-parse.adb @@ -2145,16 +2145,23 @@ package body Vhdl.Parse is Tm := Parse_Type_Mark (Check_Paren => True); - if Current_Token = Tok_Of then + if Tm /= Null_Iir and then Current_Token = Tok_Of then if Vhdl_Std < Vhdl_19 then Error_Msg_Parse ("return identifier not allowed before vhdl 2019"); + elsif Get_Kind (Tm) /= Iir_Kind_Simple_Name then + Error_Msg_Parse ("return identifier must be an identifier"); end if; - pragma Assert (Get_Kind (Tm) = Iir_Kind_Simple_Name); Ret := Create_Iir (Iir_Kind_Subtype_Declaration); Location_Copy (Ret, Tm); Set_Identifier (Ret, Get_Identifier (Tm)); - Set_Return_Identifier (Subprg, Ret); + if Get_Kind (Subprg) = Iir_Kind_Interface_Function_Declaration + then + Error_Msg_Parse + ("return identifier not allowed in interface function"); + else + Set_Return_Identifier (Subprg, Ret); + end if; Free_Iir (Tm); -- Skip 'of' @@ -6320,7 +6327,14 @@ package body Vhdl.Parse is Scan; -- Resize. - Resize_Bit_String (Res, Nat32 (Int)); + if Int > 2048 then + -- What is a reasonable limit ? + Error_Msg_Parse + (Get_Token_Location, + "bit string size is too large (> 2048)"); + else + Resize_Bit_String (Res, Nat32 (Int)); + end if; else Error_Msg_Parse (Get_Token_Location, @@ -7358,6 +7372,8 @@ package body Vhdl.Parse is | Iir_Kind_Signature => Error_Msg_Parse ("invalid name for a procedure call or missing assignment"); + when Iir_Kind_Error => + null; when others => Error_Kind ("parenthesis_name_to_procedure_call", Name); end case; @@ -10786,10 +10802,13 @@ package body Vhdl.Parse is -- Parse configuration item list declare First, Last : Iir; + Item : Iir; begin Chain_Init (First, Last); while Current_Token = Tok_For loop - Chain_Append (First, Last, Parse_Configuration_Item); + Item := Parse_Configuration_Item; + exit when Item = Null_Iir; + Chain_Append (First, Last, Item); end loop; Set_Configuration_Item_Chain (Res, First); end; @@ -11234,6 +11253,7 @@ package body Vhdl.Parse is -- Skip identifier. Scan; else + Id := Null_Identifier; Expect (Tok_Identifier); end if; @@ -11524,7 +11544,11 @@ package body Vhdl.Parse is is End_Loc : Location_Type; begin - Set_Library_Unit (Unit, Decl); + if Get_Kind (Unit) = Iir_Kind_Context_Declaration then + Error_Msg_Parse ("nested context declaration not allowed"); + else + Set_Library_Unit (Unit, Decl); + end if; -- Skip 'is' Scan; diff --git a/src/vhdl/vhdl-parse_psl.adb b/src/vhdl/vhdl-parse_psl.adb index e456514bf..d6168ca23 100644 --- a/src/vhdl/vhdl-parse_psl.adb +++ b/src/vhdl/vhdl-parse_psl.adb @@ -48,12 +48,18 @@ package body Vhdl.Parse_Psl is function Parse_Number return Node is + V : Int64; Res : Node; begin if Current_Token = Tok_Integer then Res := Create_Node_Loc (N_Number); -- FIXME: handle overflow. - Set_Value (Res, Uns32 (Current_Iir_Int64)); + V := Current_Iir_Int64; + if V > Int64 (Uns32'Last) then + Error_Msg_Parse ("number if too large"); + V := Int64 (Uns32'Last); + end if; + Set_Value (Res, Uns32 (V)); Scan; return Res; elsif Current_Token = Tok_Inf then @@ -70,9 +76,15 @@ package body Vhdl.Parse_Psl is is Low_B : constant Node := Get_Low_Bound (N); High_B : constant Node := Get_High_Bound (N); - Low : constant Uns32 := Get_Value (Low_B); + Low : Uns32; High : Uns32; begin + if Low_B = Null_Node then + -- Avoid crash on error. + return; + end if; + + Low := Get_Value (Low_B); if Get_Kind (High_B) = N_Inf then return; end if; diff --git a/src/vhdl/vhdl-post_sems.adb b/src/vhdl/vhdl-post_sems.adb index ba5a35419..cbf508f78 100644 --- a/src/vhdl/vhdl-post_sems.adb +++ b/src/vhdl/vhdl-post_sems.adb @@ -16,6 +16,7 @@ with Types; use Types; with Std_Names; use Std_Names; with Vhdl.Sem_Specs; +with Vhdl.Std_Env; with Vhdl.Ieee.Std_Logic_1164; with Vhdl.Ieee.Vital_Timing; with Vhdl.Ieee.Numeric; @@ -58,6 +59,9 @@ package body Vhdl.Post_Sems is Vhdl.Ieee.Std_Logic_1164.Extract_Declarations (Lib_Unit); when Name_VITAL_Timing => Vhdl.Ieee.Vital_Timing.Extract_Declarations (Lib_Unit); + when Name_Numeric_Bit => + Vhdl.Ieee.Numeric.Extract_Bit_Declarations + (Lib_Unit); when Name_Numeric_Std => Vhdl.Ieee.Numeric.Extract_Std_Declarations (Lib_Unit); @@ -80,6 +84,13 @@ package body Vhdl.Post_Sems is null; end case; end if; + elsif Get_Identifier (Lib) = Name_Std then + -- This is a unit of Std. + if Get_Kind (Lib_Unit) = Iir_Kind_Package_Declaration + and then Id = Name_Env + then + Vhdl.Std_Env.Extract_Declarations (Lib_Unit); + end if; end if; -- Look for VITAL attributes. diff --git a/src/vhdl/vhdl-scanner.adb b/src/vhdl/vhdl-scanner.adb index 0527cd131..a6c7b64dd 100644 --- a/src/vhdl/vhdl-scanner.adb +++ b/src/vhdl/vhdl-scanner.adb @@ -771,7 +771,7 @@ package body Vhdl.Scanner is end loop; end Add_One_To_Carries; begin - pragma Assert (Source (Pos) = '"'); + pragma Assert (Source (Pos) = '"' or Source (Pos) = '%'); Pos := Pos + 1; Length := 0; Id := Create_String8; diff --git a/src/vhdl/vhdl-sem.adb b/src/vhdl/vhdl-sem.adb index ce0428476..20b5f13ad 100644 --- a/src/vhdl/vhdl-sem.adb +++ b/src/vhdl/vhdl-sem.adb @@ -128,6 +128,9 @@ package body Vhdl.Sem is Entity := Get_Library_Unit (Entity); Set_Named_Entity (Name, Entity); Xrefs.Xref_Ref (Name, Entity); + elsif Get_Kind (Name) not in Iir_Kinds_Denoting_Name then + Error_Msg_Sem (+Name, "entity name expected"); + return Null_Iir; else -- Certainly an expanded name. Use the standard name analysis. Name := Sem_Denoting_Name (Name); @@ -566,6 +569,9 @@ package body Vhdl.Sem is -- The actual, if an expression, must be a globally -- static expression. if Get_Expr_Staticness (Actual) < Globally then + -- This is an inertial association. + Set_Inertial_Flag (Assoc, True); + if Flags.Vhdl_Std < Vhdl_08 then -- LRM08 6.5.6.3 Port clauses Error_Msg_Sem @@ -1388,20 +1394,14 @@ package body Vhdl.Sem is -- A simple name can be replaced by an expanded name in which this -- simple name is the selector, if and only if at both places the -- meaning of the simple name is given by the same declaration. - case Get_Kind (Left) is - when Iir_Kind_Simple_Name - | Iir_Kind_Selected_Name => - case Get_Kind (Right) is - when Iir_Kind_Simple_Name - | Iir_Kind_Selected_Name => - return Are_Trees_Equal (Get_Named_Entity (Left), - Get_Named_Entity (Right)); - when others => - return False; - end case; - when others => - null; - end case; + if Get_Kind (Left) in Iir_Kinds_Denoting_Name then + if Get_Kind (Right) in Iir_Kinds_Denoting_Name then + return Get_Identifier (Left) = Get_Identifier (Right) + and then Get_Named_Entity (Left) = Get_Named_Entity (Right); + else + return False; + end if; + end if; -- If nodes are not of the same kind, then they are not equals! if Get_Kind (Left) /= Get_Kind (Right) then @@ -1654,6 +1654,10 @@ package body Vhdl.Sem is (Get_Association_Choices_Chain (Left), Get_Association_Choices_Chain (Right)); + when Iir_Kind_Simple_Aggregate => + return Are_Trees_Equal (Get_Literal_Origin (Left), + Get_Literal_Origin (Right)); + when Iir_Kind_Choice_By_None | Iir_Kind_Choice_By_Others => return Are_Trees_Equal (Get_Associated_Expr (Left), @@ -1995,13 +1999,32 @@ package body Vhdl.Sem is end loop; end; - -- Mark the procedure as suspendable, unless in a std packages. + -- Mark the procedure as suspendable, unless in a std or + -- most ieee packages. -- This is a minor optimization. - if Get_Library (Get_Design_File (Get_Current_Design_Unit)) - /= Libraries.Std_Library - then - Set_Suspend_Flag (Subprg, True); - end if; + declare + Lib : constant Iir := + Get_Library (Get_Design_File (Get_Current_Design_Unit)); + begin + if Lib = Libraries.Std_Library then + -- No procedures in std have a wait statement. + null; + elsif Get_Identifier (Lib) = Std_Names.Name_Ieee then + -- Package ieee.vital_primitives has wait statements. + declare + Unit : constant Iir := + Get_Library_Unit (Get_Current_Design_Unit); + Unit_Id : constant Name_Id := Get_Identifier (Unit); + begin + if Unit_Id = Std_Names.Name_VITAL_Primitives then + Set_Suspend_Flag (Subprg, True); + end if; + end; + else + -- User procedures may have wait statements. + Set_Suspend_Flag (Subprg, True); + end if; + end; when others => Error_Kind ("sem_subprogram_declaration", Subprg); end case; @@ -2844,7 +2867,10 @@ package body Vhdl.Sem is Pkg : constant Iir := Get_Uninstantiated_Package_Decl (Inter); begin - if Get_Macro_Expanded_Flag (Pkg) then + -- Could be an error. + if Get_Kind (Pkg) = Iir_Kind_Package_Declaration + and then Get_Macro_Expanded_Flag (Pkg) + then return True; end if; end; @@ -3035,17 +3061,23 @@ package body Vhdl.Sem is Name : Iir; Pkg : Iir; begin - Name := Sem_Denoting_Name (Get_Uninstantiated_Package_Name (Decl)); - Set_Uninstantiated_Package_Name (Decl, Name); - Pkg := Get_Named_Entity (Name); - if Is_Error (Pkg) then - null; - elsif Get_Kind (Pkg) /= Iir_Kind_Package_Declaration then - Error_Class_Match (Name, "package"); - Pkg := Create_Error (Pkg); - elsif not Is_Uninstantiated_Package (Pkg) then - Error_Msg_Sem (+Name, "%n is not an uninstantiated package", +Pkg); - Pkg := Create_Error (Pkg); + Name := Get_Uninstantiated_Package_Name (Decl); + if Get_Kind (Name) not in Iir_Kinds_Denoting_Name then + Error_Msg_Sem (+Name, "uninstantiated package name expected"); + Pkg := Create_Error (Name); + else + Name := Sem_Denoting_Name (Name); + Set_Uninstantiated_Package_Name (Decl, Name); + Pkg := Get_Named_Entity (Name); + if Is_Error (Pkg) then + null; + elsif Get_Kind (Pkg) /= Iir_Kind_Package_Declaration then + Error_Class_Match (Name, "package"); + Pkg := Create_Error (Pkg); + elsif not Is_Uninstantiated_Package (Pkg) then + Error_Msg_Sem (+Name, "%n is not an uninstantiated package", +Pkg); + Pkg := Create_Error (Pkg); + end if; end if; Set_Uninstantiated_Package_Decl (Decl, Pkg); diff --git a/src/vhdl/vhdl-sem_assocs.adb b/src/vhdl/vhdl-sem_assocs.adb index a667345a2..41c93273f 100644 --- a/src/vhdl/vhdl-sem_assocs.adb +++ b/src/vhdl/vhdl-sem_assocs.adb @@ -1571,6 +1571,12 @@ package body Vhdl.Sem_Assocs is -- Analyze actual. Actual := Get_Actual (Assoc); + if Get_Kind (Actual) not in Iir_Kinds_Denoting_Name then + Error_Msg_Sem + (+Assoc, + "actual of association must denote a package instantiation"); + return; + end if; Actual := Sem_Denoting_Name (Actual); Set_Actual (Assoc, Actual); @@ -2724,7 +2730,8 @@ package body Vhdl.Sem_Assocs is Pos := 0; while Inter /= Null_Iir loop if Inter_Matched (Pos) <= Open then - if Sem_Check_Missing_Association (Inter, Missing, Finish, Loc) + if Sem_Check_Missing_Association + (Inter, Missing, Finish, Inter_Matched (Pos) = Open, Loc) then Match := Not_Compatible; if not Finish then @@ -2738,9 +2745,11 @@ package body Vhdl.Sem_Assocs is end loop; end Sem_Association_Chain; - function Sem_Check_Missing_Association - (Inter : Iir; Missing : Missing_Type; Finish : Boolean; Loc : Iir) - return Boolean + function Sem_Check_Missing_Association (Inter : Iir; + Missing : Missing_Type; + Finish : Boolean; + Is_Open : Boolean; + Loc : Iir) return Boolean is Err : Boolean; begin @@ -2770,6 +2779,10 @@ package body Vhdl.Sem_Assocs is Error_Msg_Sem (+Loc, "%n of mode IN must be connected", +Inter); Err := True; + elsif not Is_Open then + Warning_Msg_Sem + (Warnid_No_Assoc, +Loc, + "%n of mode IN is not connected", +Inter); end if; when Iir_Out_Mode | Iir_Linkage_Mode @@ -2783,6 +2796,10 @@ package body Vhdl.Sem_Assocs is (+Loc, "unconstrained %n must be connected", +Inter); Err := True; + elsif not Is_Open then + Warning_Msg_Sem + (Warnid_No_Assoc, +Loc, + "%n of mode OUT is not connected", +Inter); end if; when Iir_Unknown_Mode => raise Internal_Error; diff --git a/src/vhdl/vhdl-sem_assocs.ads b/src/vhdl/vhdl-sem_assocs.ads index f59ecb3d3..fc334d828 100644 --- a/src/vhdl/vhdl-sem_assocs.ads +++ b/src/vhdl/vhdl-sem_assocs.ads @@ -98,7 +98,9 @@ package Vhdl.Sem_Assocs is -- INTER is an interface that is known not to be associated. -- Report an error according to MISSING iff FINISH is true. -- Return True iff not associating INTER is an error. - function Sem_Check_Missing_Association - (Inter : Iir; Missing : Missing_Type; Finish : Boolean; Loc : Iir) - return Boolean; + function Sem_Check_Missing_Association (Inter : Iir; + Missing : Missing_Type; + Finish : Boolean; + Is_Open : Boolean; + Loc : Iir) return Boolean; end Vhdl.Sem_Assocs; diff --git a/src/vhdl/vhdl-sem_decls.adb b/src/vhdl/vhdl-sem_decls.adb index 282137e90..843b24123 100644 --- a/src/vhdl/vhdl-sem_decls.adb +++ b/src/vhdl/vhdl-sem_decls.adb @@ -505,6 +505,16 @@ package body Vhdl.Sem_Decls is return; end if; + if Get_Is_Within_Flag (Pkg) then + -- Looks obvious, but there is apparently no such rule in the LRM. + -- Catch error like: + -- package gen is + -- generic(package g2 is new gen generic map(<>)); + -- end; + Error_Msg_Sem (+Inter, "generic package formal cannot be itself"); + return; + end if; + if Get_Generic_Map_Aspect_Chain (Inter) /= Null_Iir then Sem_Generic_Association_Chain (Get_Package_Header (Pkg), Inter); -- Not yet fully supported - need to check the instance. diff --git a/src/vhdl/vhdl-sem_expr.adb b/src/vhdl/vhdl-sem_expr.adb index ceb7af3b3..8a7ea0d89 100644 --- a/src/vhdl/vhdl-sem_expr.adb +++ b/src/vhdl/vhdl-sem_expr.adb @@ -398,6 +398,8 @@ package body Vhdl.Sem_Expr is | Iir_Kind_Procedure_Declaration | Iir_Kind_Range_Array_Attribute | Iir_Kind_Reverse_Range_Array_Attribute + | Iir_Kind_Subtype_Attribute + | Iir_Kind_Element_Attribute | Iir_Kind_Element_Declaration | Iir_Kind_Attribute_Declaration | Iir_Kind_Psl_Declaration @@ -3560,6 +3562,31 @@ package body Vhdl.Sem_Expr is "element is out of the bounds"); end if; + if Is_Array + and then Get_Kind (El) = Iir_Kind_Choice_By_Range + then + declare + Ch_Rng : constant Iir := Get_Choice_Range (El); + Expr_Type : constant Iir := Get_Type (Expr); + Idx : Iir; + begin + if Get_Expr_Staticness (Ch_Rng) = Locally + and then Get_Index_Constraint_Flag (Expr_Type) + then + Idx := Get_Index_Type (Expr_Type, 0); + if Get_Type_Staticness (Idx) = Locally + and then (Eval_Discrete_Type_Length (Idx) + /= Eval_Discrete_Range_Length (Ch_Rng)) + then + Warning_Msg_Sem (Warnid_Runtime_Error, +Expr, + "length mismatch"); + Expr := Build_Overflow (Expr, Expr_Type); + Set_Associated_Expr (El, Expr); + end if; + end if; + end; + end if; + Expr_Staticness := Min (Expr_Staticness, El_Staticness); Info.Nbr_Assocs := Info.Nbr_Assocs + 1; diff --git a/src/vhdl/vhdl-sem_lib.adb b/src/vhdl/vhdl-sem_lib.adb index c4e26ee70..56312701b 100644 --- a/src/vhdl/vhdl-sem_lib.adb +++ b/src/vhdl/vhdl-sem_lib.adb @@ -354,9 +354,13 @@ package body Vhdl.Sem_Lib is -- Disable all warnings. Warnings are emitted only when the unit -- is analyzed. Save_Warnings_Setting (Warnings); - Disable_All_Warnings; if Get_Date_State (Design_Unit) = Date_Disk then + -- The unit is not loaded, so load it. + -- But disable warnings as the unit has already been analyzed. + -- The unit can be in memory but not yet analyzed when -c/-r is + -- used. In that case, warnings shouldn't be disabled. + Disable_All_Warnings; Load_Parse_Design_Unit (Design_Unit, Loc); end if; diff --git a/src/vhdl/vhdl-sem_names.adb b/src/vhdl/vhdl-sem_names.adb index 4ce05632f..bf195d91e 100644 --- a/src/vhdl/vhdl-sem_names.adb +++ b/src/vhdl/vhdl-sem_names.adb @@ -962,7 +962,7 @@ package body Vhdl.Sem_Names is if Get_Kind (Res) in Iir_Kinds_Denoting_Name then Set_Named_Entity (Res, Atype); else - return Create_Error_Type (Name); + Res := Create_Error_Type (Name); end if; elsif not Incomplete then if Get_Kind (Atype) = Iir_Kind_Incomplete_Type_Definition then @@ -2587,7 +2587,10 @@ package body Vhdl.Sem_Names is | Iir_Kind_Procedure_Call_Statement | Iir_Kind_Attribute_Declaration | Iir_Kind_Type_Conversion - | Iir_Kind_Element_Attribute => + | Iir_Kind_Element_Attribute + | Iir_Kind_Enumeration_Literal + | Iir_Kind_Unit_Declaration + | Iir_Kind_Variable_Assignment_Statement => if not Soft then Error_Msg_Sem (+Prefix_Loc, "%n cannot be selected by name", +Prefix); @@ -2963,6 +2966,22 @@ package body Vhdl.Sem_Names is Assoc_Chain, True, Missing_Parameter, Name, Match); end Error_Parenthesis_Function; + function Has_Error_In_Assocs (Chain : Iir) return Boolean + is + Assoc : Iir; + begin + Assoc := Chain; + while Assoc /= Null_Iir loop + if Get_Kind (Assoc) = Iir_Kind_Association_Element_By_Expression + and then Is_Error (Get_Actual (Assoc)) + then + return True; + end if; + Assoc := Get_Chain (Assoc); + end loop; + return False; + end Has_Error_In_Assocs; + Actual : Iir; Actual_Expr : Iir; begin @@ -2978,29 +2997,33 @@ package body Vhdl.Sem_Names is Assoc_Chain := Get_Association_Chain (Name); Actual := Get_One_Actual (Assoc_Chain); - if Kind_In (Prefix, - Iir_Kind_Type_Declaration, Iir_Kind_Subtype_Declaration) - then - -- A type conversion. The prefix is a type mark. - declare - In_Formal : Boolean; - begin - if Actual = Null_Iir then - -- More than one actual. Keep only the first. - Error_Msg_Sem - (+Name, "type conversion allows only one expression"); - In_Formal := False; - else - In_Formal := Get_In_Formal_Flag (Assoc_Chain); - end if; + case Get_Kind (Prefix) is + when Iir_Kind_Type_Declaration + | Iir_Kind_Subtype_Declaration + | Iir_Kind_Subtype_Attribute + | Iir_Kind_Element_Attribute => + -- A type conversion. The prefix is a type mark. + declare + In_Formal : Boolean; + begin + if Actual = Null_Iir then + -- More than one actual. Keep only the first. + Error_Msg_Sem + (+Name, "type conversion allows only one expression"); + In_Formal := False; + else + In_Formal := Get_In_Formal_Flag (Assoc_Chain); + end if; - -- This is certainly the easiest case: the prefix is not - -- overloaded, so the result can be computed. - Set_Named_Entity - (Name, Sem_Type_Conversion (Name, Prefix, Actual, In_Formal)); - end; - return; - end if; + -- This is certainly the easiest case: the prefix is not + -- overloaded, so the result can be computed. + Set_Named_Entity + (Name, Sem_Type_Conversion (Name, Prefix, Actual, In_Formal)); + end; + return; + when others => + null; + end case; -- Select between slice or indexed name. Actual_Expr := Null_Iir; @@ -3063,7 +3086,9 @@ package body Vhdl.Sem_Names is Free_Overload_List (Prefix); Set_Named_Entity (Prefix_Name, Res_Prefix); end; - if Res = Null_Iir then + if Res = Null_Iir and then not Has_Error_In_Assocs (Assoc_Chain) + then + -- Emit an error, but avoid a storm. Error_Msg_Sem (+Name, "no overloaded function found matching %n", +Prefix_Name); @@ -3352,13 +3377,11 @@ package body Vhdl.Sem_Names is Error_Msg_Sem (+Attr, "prefix of user defined attribute cannot be " & "an anonymous object"); return Error_Mark; - when Iir_Kind_Attribute_Declaration => - Error_Msg_Sem (+Attr, "prefix of user defined attribute cannot be " - & "an attribute"); - return Error_Mark; when Iir_Kind_Function_Call | Iir_Kind_Type_Conversion - | Iir_Kinds_Attribute => + | Iir_Kinds_Attribute + | Iir_Kind_Attribute_Declaration + | Iir_Kind_Library_Declaration => Error_Msg_Sem (+Attr, "invalid prefix for user defined attribute"); return Error_Mark; when Iir_Kinds_Object_Declaration @@ -3591,6 +3614,37 @@ package body Vhdl.Sem_Names is return Res; end Sem_Predefined_Type_Attribute; + function Is_Element_Attribute_Prefix_A_Type (Prefix : Iir) return Boolean + is + Pfx : Iir; + Ent : Iir; + begin + Pfx := Prefix; + loop + case Get_Kind (Pfx) is + when Iir_Kinds_Denoting_Name + | Iir_Kind_Attribute_Name => + Ent := Get_Named_Entity (Pfx); + case Get_Kind (Ent) is + when Iir_Kind_Type_Declaration + | Iir_Kind_Subtype_Declaration + | Iir_Kind_Base_Attribute => + return True; + when Iir_Kind_Element_Attribute => + -- Continue. + Pfx := Get_Prefix (Ent); + when others => + return False; + end case; + when Iir_Kind_Element_Attribute => + -- Continue + Pfx := Get_Prefix (Pfx); + when others => + return False; + end case; + end loop; + end Is_Element_Attribute_Prefix_A_Type; + -- Called for attributes Length, Left, Right, High, Low, Range, -- Reverse_Range, Ascending. -- FIXME: handle overload @@ -3602,6 +3656,7 @@ package body Vhdl.Sem_Names is Prefix : Iir; Res : Iir; Res_Type : Iir; + Is_Prefix_Object : Boolean; begin Prefix := Get_Named_Entity (Prefix_Name); @@ -3636,6 +3691,7 @@ package body Vhdl.Sem_Names is | Iir_Kind_Attribute_Value | Iir_Kind_Image_Attribute => -- FIXME: list of expr. + Is_Prefix_Object := True; Prefix_Type := Get_Type (Prefix); case Get_Kind (Prefix_Type) is when Iir_Kind_Access_Type_Definition @@ -3656,21 +3712,24 @@ package body Vhdl.Sem_Names is end case; when Iir_Kind_Subtype_Declaration | Iir_Kind_Type_Declaration - | Iir_Kind_Base_Attribute - | Iir_Kind_Subtype_Attribute - | Iir_Kind_Element_Attribute => + | Iir_Kind_Base_Attribute => + Is_Prefix_Object := False; + Prefix_Type := Get_Type (Prefix); + when Iir_Kind_Subtype_Attribute => + -- Always constrained as the prefix is an object. + Is_Prefix_Object := True; Prefix_Type := Get_Type (Prefix); - if not Is_Fully_Constrained_Type (Prefix_Type) then - Error_Msg_Sem (+Attr, "prefix type is not constrained"); - -- We continue using the unconstrained array type. - -- At least, this type is valid; and even if the array was - -- constrained, the base type would be the same. - end if; when Iir_Kind_Range_Array_Attribute - | Iir_Kind_Reverse_Range_Array_Attribute => + | Iir_Kind_Reverse_Range_Array_Attribute => -- For names such as pfx'Range'Left. - -- Finish_Sem_Array_Attribute (Prefix_Name, Prefix, Null_Iir); + Is_Prefix_Object := False; -- Doesn't matter, it's scalar. + Prefix_Type := Get_Type (Prefix); + when Iir_Kind_Element_Attribute => Prefix_Type := Get_Type (Prefix); + -- We need to know if the prefix is or denotes an object, as in + -- that case the type is constrained. + Is_Prefix_Object := + not Is_Element_Attribute_Prefix_A_Type (Prefix); when Iir_Kind_Process_Statement => Error_Msg_Sem (+Attr, "%n is not an appropriate prefix for %i attribute", @@ -3694,6 +3753,16 @@ package body Vhdl.Sem_Names is return Error_Mark; end case; + -- If the prefix is an object, we know its type is constrained. + if not Is_Prefix_Object + and then not Get_Index_Constraint_Flag (Prefix_Type) + then + Error_Msg_Sem (+Attr, "prefix type is not constrained"); + -- We continue using the unconstrained array type. + -- At least, this type is valid; and even if the array was + -- constrained, the base type would be the same. + end if; + -- Type of the attribute. This is correct unless there is a parameter, -- and furthermore 'range and 'reverse_range has to be handled -- specially because the result is a range and not a value. @@ -3801,6 +3870,7 @@ package body Vhdl.Sem_Names is -- The type defined by 'element is always constrained. Create -- a subtype if it is not. + -- NO, it isn't. The prefix can be a type. Attr_Subtype := Get_Element_Subtype (Attr_Type); if False and not Is_Fully_Constrained_Type (Attr_Subtype) then Attr_Subtype := @@ -4539,6 +4609,9 @@ package body Vhdl.Sem_Names is Sem_Attribute_Name (Name); when Iir_Kinds_External_Name => Sem_External_Name (Name); + when Iir_Kind_Signature => + Error_Msg_Sem (+Name, "signature cannot be used here"); + Set_Named_Entity (Name, Create_Error_Name (Name)); when others => Error_Kind ("sem_name", Name); end case; @@ -4944,7 +5017,8 @@ package body Vhdl.Sem_Names is Atype : Iir; begin case Get_Kind (Name) is - when Iir_Kinds_Denoting_Name => + when Iir_Kinds_Denoting_Name + | Iir_Kind_Attribute_Name => -- Common correct case. Atype := Get_Named_Entity (Name); case Get_Kind (Atype) is diff --git a/src/vhdl/vhdl-sem_psl.adb b/src/vhdl/vhdl-sem_psl.adb index f17c49791..fc2c15fab 100644 --- a/src/vhdl/vhdl-sem_psl.adb +++ b/src/vhdl/vhdl-sem_psl.adb @@ -544,7 +544,8 @@ package body Vhdl.Sem_Psl is -- always/never. Sem_Property (Prop, Top); return Prop; - when N_Eventually => + when N_Eventually + | N_Strong => Sem_Property (Prop); return Prop; when N_Clock_Event => diff --git a/src/vhdl/vhdl-sem_scopes.adb b/src/vhdl/vhdl-sem_scopes.adb index 29c355f9a..086660316 100644 --- a/src/vhdl/vhdl-sem_scopes.adb +++ b/src/vhdl/vhdl-sem_scopes.adb @@ -1116,7 +1116,8 @@ package body Vhdl.Sem_Scopes is | Iir_Kind_Signal_Attribute_Declaration => null; - when Iir_Kind_Protected_Type_Body => + when Iir_Kind_Protected_Type_Body + | Iir_Kind_Suspend_State_Declaration => -- FIXME: allowed only in debugger (if the current scope is -- within a package body) ? null; diff --git a/src/vhdl/vhdl-sem_specs.adb b/src/vhdl/vhdl-sem_specs.adb index 38a808440..e75c786fb 100644 --- a/src/vhdl/vhdl-sem_specs.adb +++ b/src/vhdl/vhdl-sem_specs.adb @@ -1268,7 +1268,11 @@ package body Vhdl.Sem_Specs is if Is_Error (Entity_Name) then return Null_Iir; end if; - Entity_Name := Sem_Denoting_Name (Get_Entity_Name (Aspect)); + if Get_Kind (Entity_Name) not in Iir_Kinds_Denoting_Name then + Error_Msg_Sem (+Entity_Name, "name of an entity expected"); + return Null_Iir; + end if; + Entity_Name := Sem_Denoting_Name (Entity_Name); Set_Entity_Name (Aspect, Entity_Name); Entity := Get_Named_Entity (Entity_Name); if Entity = Error_Mark then @@ -1350,7 +1354,7 @@ package body Vhdl.Sem_Specs is end Sem_Entity_Aspect; procedure Sem_Check_Missing_Generic_Association - (Inter_Chain : Iir; Assoc1 : Iir; Assoc2 : Iir; Loc : Iir) + (Inter_Chain : Iir; Assoc1 : Iir; Assoc2 : Iir; Loc : Iir) is Inter : Iir; Inter_Iter : Iir; @@ -1389,7 +1393,7 @@ package body Vhdl.Sem_Specs is if Get_Open_Flag (Inter) then Set_Open_Flag (Inter, False); Err := Sem_Check_Missing_Association - (Inter, Missing_Generic, True, Loc); + (Inter, Missing_Generic, True, False, Loc); end if; Inter := Get_Chain (Inter); end loop; diff --git a/src/vhdl/vhdl-sem_types.adb b/src/vhdl/vhdl-sem_types.adb index 3d77d8ab5..eb3b7e9a7 100644 --- a/src/vhdl/vhdl-sem_types.adb +++ b/src/vhdl/vhdl-sem_types.adb @@ -570,13 +570,14 @@ package body Vhdl.Sem_Types is procedure Sem_Protected_Type_Declaration (Type_Decl : Iir_Type_Declaration) is - Decl : Iir_Protected_Type_Declaration; + Decl : constant Iir_Protected_Type_Declaration := + Get_Type_Definition (Type_Decl); El : Iir; begin - Decl := Get_Type_Definition (Type_Decl); Set_Resolved_Flag (Decl, False); Set_Signal_Type_Flag (Decl, False); Set_Type_Staticness (Decl, None); + Set_Parent (Decl, Get_Parent (Type_Decl)); -- LRM 10.3 Visibility -- [...] except in the declaration of a design_unit or a protected type @@ -871,6 +872,7 @@ package body Vhdl.Sem_Types is Last_Type : Iir; El_List : constant Iir_Flist := Get_Elements_Declaration_List (Def); + Last : Integer; El : Iir; El_Type : Iir; Resolved_Flag : Boolean; @@ -889,7 +891,14 @@ package body Vhdl.Sem_Types is Composite_Found := False; Set_Signal_Type_Flag (Def, True); - for I in Flist_First .. Flist_Last (El_List) loop + if El_List = Null_Iir_Flist then + -- Avoid a crash is no elements. + Last := Flist_First - 1; + else + Last := Flist_Last (El_List); + end if; + + for I in Flist_First .. Last loop El := Get_Nth_Element (El_List, I); El_Type := Get_Subtype_Indication (El); if El_Type /= Null_Iir then @@ -1740,6 +1749,9 @@ package body Vhdl.Sem_Types is Error_Msg_Sem (+Resolution, "record resolution not allowed for array subtype"); + when Iir_Kind_Attribute_Name => + Error_Msg_Sem + (+Resolution, "%n not allowed as resolution", +Resolution); when others => Error_Kind ("sem_array_constraint(resolution)", Resolution); end case; @@ -2047,6 +2059,9 @@ package body Vhdl.Sem_Types is Error_Msg_Sem (+Resolution, "resolution indication must be an array element resolution"); + when Iir_Kind_Attribute_Name => + Error_Msg_Sem + (+Resolution, "%n not allowed as resolution", +Resolution); when others => Error_Kind ("sem_record_constraint(resolution)", Resolution); end case; @@ -2401,6 +2416,10 @@ package body Vhdl.Sem_Types is Free_Name (Def); return Type_Mark; + when Iir_Kind_Interface_Type_Definition => + Error_Msg_Sem (+Def, "interface types can't be constrained"); + return Type_Mark; + when Iir_Kind_Error => return Type_Mark; @@ -2455,7 +2474,9 @@ package body Vhdl.Sem_Types is Res := Sem_Subtype_Constraint (Def, Type_Mark, Get_Resolution_Indication (Def)); - if not Is_Error (Res) then + if not Is_Error (Res) + and then Get_Kind (Res) in Iir_Kinds_Subtype_Definition + then Set_Subtype_Type_Mark (Res, Type_Mark_Name); end if; return Res; diff --git a/src/vhdl/vhdl-std_env.adb b/src/vhdl/vhdl-std_env.adb new file mode 100644 index 000000000..03b3c364f --- /dev/null +++ b/src/vhdl/vhdl-std_env.adb @@ -0,0 +1,59 @@ +-- Nodes recognizer for ieee.math_real. +-- Copyright (C) 2019 Tristan Gingold +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <gnu.org/licenses>. + +with Types; use Types; +with Std_Names; use Std_Names; + +package body Vhdl.Std_Env is + procedure Extract_Declarations (Pkg : Iir_Package_Declaration) + is + Decl : Iir; + Predef : Iir_Predefined_Functions; + Inter : Iir; + begin + Std_Env_Pkg := Pkg; + + Decl := Get_Declaration_Chain (Pkg); + + while Decl /= Null_Iir loop + pragma Assert (Get_Kind (Decl) in Iir_Kinds_Subprogram_Declaration); + Inter := Get_Interface_Declaration_Chain (Decl); + case Get_Identifier (Decl) is + when Name_Stop => + if Inter = Null_Iir then + Predef := Iir_Predefined_Std_Env_Stop; + else + Predef := Iir_Predefined_Std_Env_Stop_Status; + pragma Assert (Get_Chain (Inter) = Null_Iir); + end if; + when Name_Finish => + if Inter = Null_Iir then + Predef := Iir_Predefined_Std_Env_Finish; + else + Predef := Iir_Predefined_Std_Env_Finish_Status; + pragma Assert (Get_Chain (Inter) = Null_Iir); + end if; + when Name_Resolution_Limit => + pragma Assert (Inter = Null_Iir); + Predef := Iir_Predefined_Std_Env_Resolution_Limit; + when others => + raise Internal_Error; + end case; + Set_Implicit_Definition (Decl, Predef); + Decl := Get_Chain (Decl); + end loop; + end Extract_Declarations; +end Vhdl.Std_Env; diff --git a/src/vhdl/vhdl-std_env.ads b/src/vhdl/vhdl-std_env.ads new file mode 100644 index 000000000..4a0c3416b --- /dev/null +++ b/src/vhdl/vhdl-std_env.ads @@ -0,0 +1,24 @@ +-- Nodes recognizer for std.env. +-- Copyright (C) 2022 Tristan Gingold +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <gnu.org/licenses>. + +with Vhdl.Nodes; use Vhdl.Nodes; + +package Vhdl.Std_Env is + Std_Env_Pkg : Iir_Package_Declaration := Null_Iir; + + -- Extract declarations from PKG (std_env). + procedure Extract_Declarations (Pkg : Iir_Package_Declaration); +end Vhdl.Std_Env; diff --git a/src/vhdl/vhdl-utils.adb b/src/vhdl/vhdl-utils.adb index 8e9d5af90..2d36c07ad 100644 --- a/src/vhdl/vhdl-utils.adb +++ b/src/vhdl/vhdl-utils.adb @@ -240,17 +240,17 @@ package body Vhdl.Utils is loop case Get_Kind (Adecl) is when Iir_Kinds_Non_Alias_Object_Declaration - | Iir_Kinds_Quantity_Declaration - | Iir_Kind_Terminal_Declaration - | Iir_Kind_Interface_Quantity_Declaration - | Iir_Kind_Interface_Terminal_Declaration - | Iir_Kind_Interface_Type_Declaration - | Iir_Kind_Interface_Package_Declaration - | Iir_Kind_Interface_Function_Declaration - | Iir_Kind_Interface_Procedure_Declaration - | Iir_Kind_External_Signal_Name - | Iir_Kind_External_Constant_Name - | Iir_Kind_External_Variable_Name => + | Iir_Kinds_Quantity_Declaration + | Iir_Kind_Terminal_Declaration + | Iir_Kind_Interface_Quantity_Declaration + | Iir_Kind_Interface_Terminal_Declaration + | Iir_Kind_Interface_Type_Declaration + | Iir_Kind_Interface_Package_Declaration + | Iir_Kind_Interface_Function_Declaration + | Iir_Kind_Interface_Procedure_Declaration + | Iir_Kind_External_Signal_Name + | Iir_Kind_External_Constant_Name + | Iir_Kind_External_Variable_Name => return Adecl; when Iir_Kind_Object_Alias_Declaration => if With_Alias then @@ -259,35 +259,36 @@ package body Vhdl.Utils is return Adecl; end if; when Iir_Kind_Indexed_Name - | Iir_Kind_Slice_Name - | Iir_Kind_Selected_Element - | Iir_Kind_Selected_By_All_Name => + | Iir_Kind_Slice_Name + | Iir_Kind_Selected_Element + | Iir_Kind_Selected_By_All_Name => Adecl := Get_Base_Name (Adecl); when Iir_Kinds_Literal - | Iir_Kind_Overflow_Literal - | Iir_Kind_Enumeration_Literal - | Iir_Kinds_Monadic_Operator - | Iir_Kinds_Dyadic_Operator - | Iir_Kind_Function_Call - | Iir_Kind_Qualified_Expression - | Iir_Kind_Type_Conversion - | Iir_Kind_Allocator_By_Expression - | Iir_Kind_Allocator_By_Subtype - | Iir_Kind_Parenthesis_Expression - | Iir_Kinds_Attribute - | Iir_Kind_Attribute_Value - | Iir_Kind_Aggregate - | Iir_Kind_Simple_Aggregate - | Iir_Kind_Dereference - | Iir_Kind_Implicit_Dereference - | Iir_Kind_Unit_Declaration - | Iir_Kind_Psl_Expression - | Iir_Kinds_Concurrent_Statement - | Iir_Kinds_Sequential_Statement - | Iir_Kinds_Simultaneous_Statement => + | Iir_Kind_Overflow_Literal + | Iir_Kind_Enumeration_Literal + | Iir_Kinds_Monadic_Operator + | Iir_Kinds_Dyadic_Operator + | Iir_Kind_Function_Call + | Iir_Kind_Qualified_Expression + | Iir_Kind_Type_Conversion + | Iir_Kind_Allocator_By_Expression + | Iir_Kind_Allocator_By_Subtype + | Iir_Kind_Parenthesis_Expression + | Iir_Kinds_Attribute + | Iir_Kind_Attribute_Value + | Iir_Kind_Aggregate + | Iir_Kind_Simple_Aggregate + | Iir_Kind_Dereference + | Iir_Kind_Implicit_Dereference + | Iir_Kind_Unit_Declaration + | Iir_Kind_Psl_Expression + | Iir_Kinds_Concurrent_Statement + | Iir_Kinds_Sequential_Statement + | Iir_Kinds_Simultaneous_Statement + | Iir_Kind_Suspend_State_Statement => return Adecl; when Iir_Kind_Simple_Name - | Iir_Kind_Selected_Name => + | Iir_Kind_Selected_Name => Adecl := Get_Named_Entity (Adecl); when Iir_Kind_Attribute_Name => return Get_Named_Entity (Adecl); @@ -323,6 +324,7 @@ package body Vhdl.Utils is | Iir_Kind_Group_Template_Declaration | Iir_Kind_Group_Declaration | Iir_Kind_Signal_Attribute_Declaration + | Iir_Kind_Suspend_State_Declaration | Iir_Kind_Unaffected_Waveform | Iir_Kind_Waveform_Element | Iir_Kind_Conditional_Waveform @@ -674,6 +676,12 @@ package body Vhdl.Utils is end case; end Is_Parameter; + function Is_Copyback_Parameter (Inter : Iir) return Boolean is + begin + return Get_Kind (Inter) = Iir_Kind_Interface_Variable_Declaration + and then Get_Mode (Inter) in Iir_Out_Mode .. Iir_Inout_Mode; + end Is_Copyback_Parameter; + function Find_Name_In_Flist (List : Iir_Flist; Lit : Name_Id) return Iir is El : Iir; @@ -1222,6 +1230,8 @@ package body Vhdl.Utils is | Iir_Kind_Across_Attribute | Iir_Kind_Through_Attribute => return Get_Type (Ind); + when Iir_Kind_Interface_Type_Definition => + return Ind; when Iir_Kind_Error => return Ind; when others => diff --git a/src/vhdl/vhdl-utils.ads b/src/vhdl/vhdl-utils.ads index f51599cdf..01425a157 100644 --- a/src/vhdl/vhdl-utils.ads +++ b/src/vhdl/vhdl-utils.ads @@ -112,6 +112,10 @@ package Vhdl.Utils is -- Return True iff interface INTER is a (subprogram) parameter. function Is_Parameter (Inter : Iir) return Boolean; + -- Return True iff parameter INTER should be copied back (for out/inout + -- variable). + function Is_Copyback_Parameter (Inter : Iir) return Boolean; + -- Duplicate enumeration literal LIT. function Copy_Enumeration_Literal (Lit : Iir) return Iir; |