aboutsummaryrefslogtreecommitdiffstats
path: root/src/vhdl
diff options
context:
space:
mode:
Diffstat (limited to 'src/vhdl')
-rw-r--r--src/vhdl/iirs.ads4
-rw-r--r--src/vhdl/scanner.adb2
-rw-r--r--src/vhdl/sem.adb2
-rw-r--r--src/vhdl/sem_expr.adb6
-rw-r--r--src/vhdl/sem_names.ads2
-rw-r--r--src/vhdl/sem_specs.adb2
-rw-r--r--src/vhdl/simulate/simul-elaboration.adb11
-rw-r--r--src/vhdl/translate/trans-chap12.adb2
-rw-r--r--src/vhdl/translate/trans-chap7.adb2
9 files changed, 17 insertions, 16 deletions
diff --git a/src/vhdl/iirs.ads b/src/vhdl/iirs.ads
index b2cfeb5fa..47b7cf2cc 100644
--- a/src/vhdl/iirs.ads
+++ b/src/vhdl/iirs.ads
@@ -5930,7 +5930,7 @@ package Iirs is
function Get_Analysis_Checks_List (Unit : Iir) return Iir_List;
procedure Set_Analysis_Checks_List (Unit : Iir; List : Iir_List);
- -- Wether the unit is on disk, parsed or analyzed.
+ -- Whether the unit is on disk, parsed or analyzed.
-- Field: State1 (pos)
function Get_Date_State (Unit : Iir_Design_Unit) return Date_State_Type;
procedure Set_Date_State (Unit : Iir_Design_Unit; State : Date_State_Type);
@@ -6778,7 +6778,7 @@ package Iirs is
function Get_Wait_State (Proc : Iir) return Tri_State_Type;
procedure Set_Wait_State (Proc : Iir; State : Tri_State_Type);
- -- Get/Set wether the subprogram may be called by a sensitized process
+ -- Get/Set whether the subprogram may be called by a sensitized process
-- whose sensitivity list is ALL.
-- FALSE if declared in a package unit and reads a signal that is not
-- one of its interface, or if it calls such a subprogram.
diff --git a/src/vhdl/scanner.adb b/src/vhdl/scanner.adb
index c52714c17..f91357922 100644
--- a/src/vhdl/scanner.adb
+++ b/src/vhdl/scanner.adb
@@ -1670,7 +1670,7 @@ package body Scanner is
-- A comment can appear on any line line of a VHDL
-- description.
-- The presence or absence of comments has no influence on
- -- wether a description is legal or illegal.
+ -- whether a description is legal or illegal.
-- Futhermore, comments do not influence the execution of a
-- simulation module; their sole purpose is the enlightenment
-- of the human reader.
diff --git a/src/vhdl/sem.adb b/src/vhdl/sem.adb
index a19d66179..ec9542f97 100644
--- a/src/vhdl/sem.adb
+++ b/src/vhdl/sem.adb
@@ -630,7 +630,7 @@ package body Sem is
-- LRM93 10.2
-- In addition to the above rules, the scope of any declaration that
- -- includes the end of the declarative part of a given block (wether
+ -- includes the end of the declarative part of a given block (whether
-- it be an external block defined by a design entity or an internal
-- block defined by a block statement) extends into a configuration
-- declaration that configures the given block.
diff --git a/src/vhdl/sem_expr.adb b/src/vhdl/sem_expr.adb
index 11b4e544c..a33212839 100644
--- a/src/vhdl/sem_expr.adb
+++ b/src/vhdl/sem_expr.adb
@@ -2322,9 +2322,9 @@ package body Sem_Expr is
-- LRM 8.8
--
-- If the expression is the name of an object whose subtype is locally
- -- static, wether a scalar type or an array type, then each value of the
- -- subtype must be represented once and only once in the set of choices
- -- of the case statement and no other value is allowed; [...]
+ -- static, whether a scalar type or an array type, then each value of
+ -- the subtype must be represented once and only once in the set of
+ -- choices of the case statement and no other value is allowed; [...]
-- 1. Allocate Arr, fill it and sort
Count_Choices (Info, Choice_Chain);
diff --git a/src/vhdl/sem_names.ads b/src/vhdl/sem_names.ads
index 636dc884e..0e27a8c49 100644
--- a/src/vhdl/sem_names.ads
+++ b/src/vhdl/sem_names.ads
@@ -81,7 +81,7 @@ package Sem_Names is
-- Convert name NAME to an expression (ie, can create function call).
-- A_TYPE is the expected type of the expression.
- -- FIXME: it is unclear wether the result must be an expression or not
+ -- FIXME: it is unclear whether the result must be an expression or not
-- (ie, it *must* have a type, but may be a range).
function Name_To_Expression (Name : Iir; A_Type : Iir) return Iir;
diff --git a/src/vhdl/sem_specs.adb b/src/vhdl/sem_specs.adb
index af5d1c3a4..6e28c5b39 100644
--- a/src/vhdl/sem_specs.adb
+++ b/src/vhdl/sem_specs.adb
@@ -249,7 +249,7 @@ package body Sem_Specs is
-- a given named entity.
-- LRM 5.1
-- Similarly, it is an error if two different attributes with the
- -- same simple name (wether predefined or user-defined) are both
+ -- same simple name (whether predefined or user-defined) are both
-- associated with a given named entity.
Attr_Chain_Parent := Get_Attribute_Value_Chain_Parent (Decl);
El := Get_Attribute_Value_Chain (Attr_Chain_Parent);
diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb
index 73a31b287..1e71d7c4f 100644
--- a/src/vhdl/simulate/simul-elaboration.adb
+++ b/src/vhdl/simulate/simul-elaboration.adb
@@ -1493,7 +1493,7 @@ package body Simul.Elaboration is
(Ninstance, Get_Concurrent_Statement_Chain (Block));
-- Elaboration of a block statement may occur under the control of a
-- configuration declaration.
- -- In particular, a block configuration, wether implicit or explicit,
+ -- In particular, a block configuration, whether implicit or explicit,
-- within a configuration declaration may supply a sequence of
-- additionnal implicit configuration specification to be applied
-- during the elaboration of the corresponding block statement.
@@ -1503,10 +1503,11 @@ package body Simul.Elaboration is
-- is elaborated as part of the block declarative part, following all
-- other declarative items in that part.
-- The sequence of implicit configuration specifications supplied by a
- -- block configuration, wether implicit or explicit, consists of each of
- -- the configuration specifications implied by component configurations
- -- occurring immediatly within the block configuration, and in the
- -- order in which the component configurations themselves appear.
+ -- block configuration, whether implicit or explicit, consists of each
+ -- of the configuration specifications implied by component
+ -- configurations occurring immediatly within the block configuration,
+ -- and in the order in which the component configurations themselves
+ -- appear.
-- FIXME.
end Elaborate_Block_Statement;
diff --git a/src/vhdl/translate/trans-chap12.adb b/src/vhdl/translate/trans-chap12.adb
index 9a2d7022e..cad732752 100644
--- a/src/vhdl/translate/trans-chap12.adb
+++ b/src/vhdl/translate/trans-chap12.adb
@@ -708,7 +708,7 @@ package body Trans.Chap12 is
-- Generate code to elaboration body-less package.
--
- -- When a package is analyzed, we don't know wether there is body
+ -- When a package is analyzed, we don't know whether there is body
-- or not. Therefore, we assume there is always a body, and will
-- elaborate the body (which elaborates its spec). If a package
-- has no body, create the body elaboration procedure.
diff --git a/src/vhdl/translate/trans-chap7.adb b/src/vhdl/translate/trans-chap7.adb
index 67ef4bed3..e83cbfe04 100644
--- a/src/vhdl/translate/trans-chap7.adb
+++ b/src/vhdl/translate/trans-chap7.adb
@@ -1215,7 +1215,7 @@ package body Trans.Chap7 is
procedure Walk_Concat (Imp : Iir; L, R : Iir);
-- Call handlers for each leaf of E (an array expression). First
- -- check wether E is also a concatenation.
+ -- check whether E is also a concatenation.
procedure Walk_Arr (E : Iir)
is
Imp : Iir;