diff options
Diffstat (limited to 'src/vhdl')
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_unsigned.adb | 52 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-std_logic_unsigned.ads | 7 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 13 | ||||
| -rw-r--r-- | src/vhdl/vhdl-post_sems.adb | 6 |
4 files changed, 64 insertions, 14 deletions
diff --git a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb index 7e2b86c02..9e2bb5269 100644 --- a/src/vhdl/vhdl-ieee-std_logic_unsigned.adb +++ b/src/vhdl/vhdl-ieee-std_logic_unsigned.adb @@ -27,6 +27,9 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is type Binary_Pattern_Type is array (Args_Kind) of Iir_Predefined_Functions; + None_Patterns : constant Binary_Pattern_Type := + (others => Iir_Predefined_None); + Eq_Patterns : constant Binary_Pattern_Type := (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Slv_Slv, Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Slv_Int, @@ -51,23 +54,38 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Le_Int_Slv, others => Iir_Predefined_None); - Add_Patterns : constant Binary_Pattern_Type := + Add_Uns_Patterns : constant Binary_Pattern_Type := (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Slv, Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Int, Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Int_Slv, Arg_Slv_Sl => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Slv_Sl, Arg_Sl_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Add_Sl_Slv); - Sub_Patterns : constant Binary_Pattern_Type := + Sub_Uns_Patterns : constant Binary_Pattern_Type := (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Slv, Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Int, Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Int_Slv, Arg_Slv_Sl => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Slv_Sl, Arg_Sl_Slv => Iir_Predefined_Ieee_Std_Logic_Unsigned_Sub_Sl_Slv); + Add_Sgn_Patterns : constant Binary_Pattern_Type := + (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Slv, + Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Int, + Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Int_Slv, + Arg_Slv_Sl => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Sl, + Arg_Sl_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Add_Sl_Slv); + + Sub_Sgn_Patterns : constant Binary_Pattern_Type := + (Arg_Slv_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Slv, + Arg_Slv_Int => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Int, + Arg_Int_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Int_Slv, + Arg_Slv_Sl => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Sl, + Arg_Sl_Slv => Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Sl_Slv); + Error : exception; - procedure Extract_Declarations (Pkg : Iir_Package_Declaration) + procedure Extract_Declarations + (Pkg : Iir_Package_Declaration; Sign : Sign_Kind) is procedure Classify_Arg (Arg : Iir; Kind : out Arg_Kind) is @@ -89,7 +107,9 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is Arg1, Arg2 : Iir; Arg1_Kind, Arg2_Kind : Arg_Kind; - procedure Handle_Binary (Pats : Binary_Pattern_Type) + function Handle_Binary (Unsigned_Pats : Binary_Pattern_Type; + Signed_Pats : Binary_Pattern_Type) + return Iir_Predefined_Functions is Kind : Args_Kind; begin @@ -114,8 +134,15 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is end case; end case; - Set_Implicit_Definition (Decl, Pats (Kind)); + case Sign is + when Pkg_Unsigned => + return Unsigned_Pats (Kind); + when Pkg_Signed => + return Signed_Pats (Kind); + end case; end Handle_Binary; + + Res : Iir_Predefined_Functions; begin Decl := Get_Declaration_Chain (Pkg); @@ -130,6 +157,8 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is raise Error; end if; + Res := Iir_Predefined_None; + Classify_Arg (Arg1, Arg1_Kind); Arg2 := Get_Chain (Arg1); if Is_Valid (Arg2) then @@ -138,17 +167,17 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is case Get_Identifier (Decl) is when Name_Op_Equality => - Handle_Binary (Eq_Patterns); + Res := Handle_Binary (Eq_Patterns, None_Patterns); when Name_Op_Inequality => - Handle_Binary (Ne_Patterns); + Res := Handle_Binary (Ne_Patterns, None_Patterns); when Name_Op_Less => - Handle_Binary (Lt_Patterns); + Res := Handle_Binary (Lt_Patterns, None_Patterns); when Name_Op_Less_Equal => - Handle_Binary (Le_Patterns); + Res := Handle_Binary (Le_Patterns, None_Patterns); when Name_Op_Plus => - Handle_Binary (Add_Patterns); + Res := Handle_Binary (Add_Uns_Patterns, Add_Sgn_Patterns); when Name_Op_Minus => - Handle_Binary (Sub_Patterns); + Res := Handle_Binary (Sub_Uns_Patterns, Sub_Sgn_Patterns); when others => null; end case; @@ -159,6 +188,7 @@ package body Vhdl.Ieee.Std_Logic_Unsigned is null; end case; end if; + Set_Implicit_Definition (Decl, Res); Decl := Get_Chain (Decl); end loop; end Extract_Declarations; diff --git a/src/vhdl/vhdl-ieee-std_logic_unsigned.ads b/src/vhdl/vhdl-ieee-std_logic_unsigned.ads index 8ad54fd05..1e8cca5be 100644 --- a/src/vhdl/vhdl-ieee-std_logic_unsigned.ads +++ b/src/vhdl/vhdl-ieee-std_logic_unsigned.ads @@ -1,4 +1,4 @@ --- Nodes recognizer for ieee.std_logic_unsigned +-- Nodes recognizer for ieee.std_logic_unsigned and ieee.std_logic_signed. -- Copyright (C) 2019 Tristan Gingold -- -- GHDL is free software; you can redistribute it and/or modify it under @@ -17,6 +17,9 @@ -- 02111-1307, USA. package Vhdl.Ieee.Std_Logic_Unsigned is + type Sign_Kind is (Pkg_Unsigned, Pkg_Signed); + -- Extract declarations from PKG . - procedure Extract_Declarations (Pkg : Iir_Package_Declaration); + procedure Extract_Declarations + (Pkg : Iir_Package_Declaration; Sign : Sign_Kind); end Vhdl.Ieee.Std_Logic_Unsigned; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index f903a4c4d..44d25880d 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5093,6 +5093,19 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Slv_Int, Iir_Predefined_Ieee_Std_Logic_Unsigned_Ne_Int_Slv, + -- Std_Logic_Signed (synopsys extension). + Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Int, + Iir_Predefined_Ieee_Std_Logic_Signed_Add_Int_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Add_Slv_Sl, + Iir_Predefined_Ieee_Std_Logic_Signed_Add_Sl_Slv, + + Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Int, + Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Int_Slv, + Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Slv_Sl, + Iir_Predefined_Ieee_Std_Logic_Signed_Sub_Sl_Slv, + -- std_logic_arith (synopsys extention). Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int, Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Uns, diff --git a/src/vhdl/vhdl-post_sems.adb b/src/vhdl/vhdl-post_sems.adb index e5805ea59..8924a1d45 100644 --- a/src/vhdl/vhdl-post_sems.adb +++ b/src/vhdl/vhdl-post_sems.adb @@ -63,7 +63,11 @@ package body Vhdl.Post_Sems is when Name_Math_Real => Vhdl.Ieee.Math_Real.Extract_Declarations (Lib_Unit); when Name_Std_Logic_Unsigned => - Vhdl.Ieee.Std_Logic_Unsigned.Extract_Declarations (Lib_Unit); + Vhdl.Ieee.Std_Logic_Unsigned.Extract_Declarations + (Lib_Unit, Vhdl.Ieee.Std_Logic_Unsigned.Pkg_Unsigned); + when Name_Std_Logic_Signed => + Vhdl.Ieee.Std_Logic_Unsigned.Extract_Declarations + (Lib_Unit, Vhdl.Ieee.Std_Logic_Unsigned.Pkg_Signed); when Name_Std_Logic_Arith => Vhdl.Ieee.Std_Logic_Arith.Extract_Declarations (Lib_Unit); when others => |