diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/ghdldrv/ghdlsynth.adb | 2 | ||||
| -rw-r--r-- | src/std_names.adb | 1 | ||||
| -rw-r--r-- | src/std_names.ads | 3 | ||||
| -rw-r--r-- | src/synth/netlists-cleanup.adb | 29 | ||||
| -rw-r--r-- | src/synth/netlists-disp_verilog.adb | 4 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 3 | ||||
| -rw-r--r-- | src/vhdl/vhdl-parse.adb | 12 |
7 files changed, 46 insertions, 8 deletions
diff --git a/src/ghdldrv/ghdlsynth.adb b/src/ghdldrv/ghdlsynth.adb index 5d76355aa..2bff76e04 100644 --- a/src/ghdldrv/ghdlsynth.adb +++ b/src/ghdldrv/ghdlsynth.adb @@ -124,7 +124,7 @@ package body Ghdlsynth is P (" -gNAME=VALUE"); P (" Override the generic NAME of the top unit"); P (" --vendor-library=NAME"); - P (" Any unit from library NAME is a black boxe"); + P (" Any unit from library NAME is a black box"); P (" --no-formal"); P (" Neither synthesize assert nor PSL"); P (" --no-assert-cover"); diff --git a/src/std_names.adb b/src/std_names.adb index ffbfce1ef..ceabfec97 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -685,6 +685,7 @@ package body Std_Names is Def ("anyseq", Name_Anyseq); Def ("gclk", Name_Gclk); Def ("loc", Name_Loc); + Def ("keep", Name_Keep); -- Verilog directives Def ("define", Name_Define); diff --git a/src/std_names.ads b/src/std_names.ads index 45558cb48..4022a7493 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -770,7 +770,8 @@ package Std_Names is Name_Anyseq : constant Name_Id := Name_First_Synthesis + 003; Name_Gclk : constant Name_Id := Name_First_Synthesis + 004; Name_Loc : constant Name_Id := Name_First_Synthesis + 005; - Name_Last_Synthesis : constant Name_Id := Name_Loc; + Name_Keep : constant Name_Id := Name_First_Synthesis + 006; + Name_Last_Synthesis : constant Name_Id := Name_Keep; -- Verilog Directives. Name_First_Directive : constant Name_Id := Name_Last_Synthesis + 1; diff --git a/src/synth/netlists-cleanup.adb b/src/synth/netlists-cleanup.adb index d7d74b83d..8436793a8 100644 --- a/src/synth/netlists-cleanup.adb +++ b/src/synth/netlists-cleanup.adb @@ -16,6 +16,8 @@ -- You should have received a copy of the GNU General Public License -- along with this program. If not, see <gnu.org/licenses>. +with Std_Names; + with Netlists.Utils; use Netlists.Utils; with Netlists.Gates; @@ -169,6 +171,28 @@ package body Netlists.Cleanup is end loop; end Remove_Output_Gates; + function Has_Keep (Inst : Instance) return Boolean + is + Attr : Attribute; + Val : Pval; + begin + if not Has_Attribute (Inst) then + return False; + end if; + + Attr := Get_First_Attribute (Inst); + while Attr /= No_Attribute loop + if Get_Attribute_Name (Attr) = Std_Names.Name_Keep then + Val := Get_Attribute_Pval (Attr); + pragma Assert (Get_Pval_Length (Val) = 1); + return Read_Pval (Val, 0) = (1, 0); + end if; + Attr := Get_Attribute_Next (Attr); + end loop; + + return False; + end Has_Keep; + procedure Insert_Mark_And_Sweep (Inspect : in out Instance_Tables.Instance; Inst : Instance) is begin @@ -205,6 +229,11 @@ package body Netlists.Cleanup is | Id_User_Parameters => -- Always keep user modules. Insert_Mark_And_Sweep (Inspect, Inst); + when Id_Signal + | Id_Isignal => + if Has_Keep (Inst) then + Insert_Mark_And_Sweep (Inspect, Inst); + end if; when others => null; end case; diff --git a/src/synth/netlists-disp_verilog.adb b/src/synth/netlists-disp_verilog.adb index 26c511480..28d473a89 100644 --- a/src/synth/netlists-disp_verilog.adb +++ b/src/synth/netlists-disp_verilog.adb @@ -236,9 +236,7 @@ package body Netlists.Disp_Verilog is I : Input; begin I := Get_First_Sink (O); - if I = No_Input then - Put ("open"); - else + if I /= No_Input then Disp_Net_Name (O); end if; end; diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index 2634af688..bfa3db4be 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -3749,7 +3749,8 @@ package body Synth.Vhdl_Stmts is Synth_Attribute_Formal (Syn_Inst, Val, Id_Anyconst); when Name_Anyseq => Synth_Attribute_Formal (Syn_Inst, Val, Id_Anyseq); - when Name_Loc => + when Name_Loc + | Name_Keep => -- Applies to nets/ports. null; when others => diff --git a/src/vhdl/vhdl-parse.adb b/src/vhdl/vhdl-parse.adb index 01c8df6ca..6a6f67024 100644 --- a/src/vhdl/vhdl-parse.adb +++ b/src/vhdl/vhdl-parse.adb @@ -5457,7 +5457,8 @@ package body Vhdl.Parse is | Iir_Kind_Package_Body | Iir_Kind_Protected_Type_Body | Iir_Kind_Protected_Type_Declaration - | Iir_Kind_Simultaneous_Procedural_Statement => + | Iir_Kind_Simultaneous_Procedural_Statement + | Iir_Kind_Vunit_Declaration => Error_Msg_Parse ("configuration specification not allowed here"); when Iir_Kind_Architecture_Body @@ -11301,7 +11302,6 @@ package body Vhdl.Parse is | Tok_Impure | Tok_Procedure | Tok_Alias - | Tok_For | Tok_Attribute | Tok_Disconnect | Tok_Use @@ -11318,6 +11318,14 @@ package body Vhdl.Parse is Vhdl.Scanner.Flag_Psl := False; Item := Parse_Declaration (Res, Res); + when Tok_For => + Vhdl.Scanner.Flag_Psl := False; + if Label = Null_Identifier then + Item := Parse_Declaration (Res, Res); + else + Item := Parse_Concurrent_Statement (Res, Label); + end if; + when Tok_End | Tok_Eof | Tok_Right_Curly => |