diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/std_names.adb | 2 | ||||
| -rw-r--r-- | src/std_names.ads | 8 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-numeric.adb | 19 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 5 |
4 files changed, 31 insertions, 3 deletions
diff --git a/src/std_names.adb b/src/std_names.adb index 34aae433c..7552a4097 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -642,6 +642,8 @@ package body Std_Names is Def ("to_signed", Name_To_Signed); Def ("resize", Name_Resize); Def ("std_match", Name_Std_Match); + Def ("shift_left", Name_Shift_Left); + Def ("shift_right", Name_Shift_Right); Def ("math_real", Name_Math_Real); Def ("ceil", Name_Ceil); Def ("log2", Name_Log2); diff --git a/src/std_names.ads b/src/std_names.ads index e20db31a9..3af9e6082 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -723,9 +723,11 @@ package Std_Names is Name_To_Signed : constant Name_Id := Name_First_Ieee + 021; Name_Resize : constant Name_Id := Name_First_Ieee + 022; Name_Std_Match : constant Name_Id := Name_First_Ieee + 023; - Name_Math_Real : constant Name_Id := Name_First_Ieee + 024; - Name_Ceil : constant Name_Id := Name_First_Ieee + 025; - Name_Log2 : constant Name_Id := Name_First_Ieee + 026; + Name_Shift_Left : constant Name_Id := Name_First_Ieee + 024; + Name_Shift_Right : constant Name_Id := Name_First_Ieee + 025; + Name_Math_Real : constant Name_Id := Name_First_Ieee + 026; + Name_Ceil : constant Name_Id := Name_First_Ieee + 027; + Name_Log2 : constant Name_Id := Name_First_Ieee + 028; Name_Last_Ieee : constant Name_Id := Name_Log2; -- Verilog Directives. diff --git a/src/vhdl/vhdl-ieee-numeric.adb b/src/vhdl/vhdl-ieee-numeric.adb index 4d5c0d5e3..500c0a260 100644 --- a/src/vhdl/vhdl-ieee-numeric.adb +++ b/src/vhdl/vhdl-ieee-numeric.adb @@ -477,6 +477,8 @@ package body Vhdl.Ieee.Numeric is Set_Implicit_Definition (Decl, Predefined); end Handle_Std_Match; + + Res : Iir_Predefined_Functions; begin Decl := Get_Declaration_Chain (Pkg_Decl); @@ -589,6 +591,23 @@ package body Vhdl.Ieee.Numeric is Handle_Resize; when Name_Std_Match => Handle_Std_Match; + when Name_Shift_Left => + if Arg1_Kind = Arg_Vect + and then Arg2_Kind = Arg_Scal + and then Arg2_Sign = Type_Unsigned + then + case Arg1_Sign is + when Type_Signed => + Res := + Iir_Predefined_Ieee_Numeric_Std_Shl_Sgn_Nat; + when Type_Unsigned => + Res := + Iir_Predefined_Ieee_Numeric_Std_Shl_Uns_Nat; + when others => + Res := Iir_Predefined_None; + end case; + Set_Implicit_Definition (Decl, Res); + end if; when others => null; end case; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 93407a5df..de1df09e9 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -4992,6 +4992,11 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Numeric_Std_Ne_Sgn_Int, Iir_Predefined_Ieee_Numeric_Std_Ne_Int_Sgn, + Iir_Predefined_Ieee_Numeric_Std_Shl_Uns_Nat, + Iir_Predefined_Ieee_Numeric_Std_Shr_Uns_Nat, + Iir_Predefined_Ieee_Numeric_Std_Shl_Sgn_Nat, + Iir_Predefined_Ieee_Numeric_Std_Shr_Sgn_Nat, + Iir_Predefined_Ieee_Numeric_Std_Not_Uns, Iir_Predefined_Ieee_Numeric_Std_Not_Sgn, |