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-rw-r--r--src/ghdldrv/ghdl_llvm.adb2
-rw-r--r--src/std_names.adb1
-rw-r--r--src/std_names.ads7
-rw-r--r--src/synth/ghdlsynth_gates.h9
-rw-r--r--src/synth/netlists-gates.ads9
-rw-r--r--src/synth/synth-expr.adb13
-rw-r--r--src/synth/synth-stmts.adb4
-rw-r--r--src/vhdl/vhdl-annotations.adb8
-rw-r--r--src/vhdl/vhdl-ieee-numeric.adb32
-rw-r--r--src/vhdl/vhdl-ieee-std_logic_1164.adb20
-rw-r--r--src/vhdl/vhdl-nodes.ads9
11 files changed, 87 insertions, 27 deletions
diff --git a/src/ghdldrv/ghdl_llvm.adb b/src/ghdldrv/ghdl_llvm.adb
index c170c4b56..f18741bd6 100644
--- a/src/ghdldrv/ghdl_llvm.adb
+++ b/src/ghdldrv/ghdl_llvm.adb
@@ -21,6 +21,7 @@ with Ghdlprint;
with Ghdldrv;
with Ghdlvpi;
with Ghdlxml;
+with Ghdlsynth_Maybe;
procedure Ghdl_Llvm is
begin
@@ -29,6 +30,7 @@ begin
Ghdlmain.Version_String := new String'("llvm code generator");
Ghdldrv.Backend := Ghdldrv.Backend_Llvm;
Ghdldrv.Register_Commands;
+ Ghdlsynth_Maybe.Register_Commands;
Ghdllocal.Register_Commands;
Ghdlprint.Register_Commands;
Ghdlvpi.Register_Commands;
diff --git a/src/std_names.adb b/src/std_names.adb
index bdc11e695..34aae433c 100644
--- a/src/std_names.adb
+++ b/src/std_names.adb
@@ -641,6 +641,7 @@ package body Std_Names is
Def ("to_unsigned", Name_To_Unsigned);
Def ("to_signed", Name_To_Signed);
Def ("resize", Name_Resize);
+ Def ("std_match", Name_Std_Match);
Def ("math_real", Name_Math_Real);
Def ("ceil", Name_Ceil);
Def ("log2", Name_Log2);
diff --git a/src/std_names.ads b/src/std_names.ads
index a00d89585..e20db31a9 100644
--- a/src/std_names.ads
+++ b/src/std_names.ads
@@ -722,9 +722,10 @@ package Std_Names is
Name_To_Unsigned : constant Name_Id := Name_First_Ieee + 020;
Name_To_Signed : constant Name_Id := Name_First_Ieee + 021;
Name_Resize : constant Name_Id := Name_First_Ieee + 022;
- Name_Math_Real : constant Name_Id := Name_First_Ieee + 023;
- Name_Ceil : constant Name_Id := Name_First_Ieee + 024;
- Name_Log2 : constant Name_Id := Name_First_Ieee + 025;
+ Name_Std_Match : constant Name_Id := Name_First_Ieee + 023;
+ Name_Math_Real : constant Name_Id := Name_First_Ieee + 024;
+ Name_Ceil : constant Name_Id := Name_First_Ieee + 025;
+ Name_Log2 : constant Name_Id := Name_First_Ieee + 026;
Name_Last_Ieee : constant Name_Id := Name_Log2;
-- Verilog Directives.
diff --git a/src/synth/ghdlsynth_gates.h b/src/synth/ghdlsynth_gates.h
index a8dfe2a7f..bef7a7d97 100644
--- a/src/synth/ghdlsynth_gates.h
+++ b/src/synth/ghdlsynth_gates.h
@@ -1,4 +1,5 @@
-/* This file is automatically generated by build_header.sh - DO NOT MODIFY */
+/* DO NOT MODIFY
+ This file is automatically generated by Makefile. */
enum Module_Id {
Id_None = 0,
Id_Free = 1,
@@ -57,12 +58,8 @@ enum Module_Id {
Id_Assume = 57,
Id_Const_UB32 = 64,
Id_Const_UL32 = 70,
- Id_Const_SB32 = 65,
Id_Const_UB64 = 66,
- Id_Const_SB64 = 67,
- Id_Const_UB128 = 68,
- Id_Const_SB128 = 69,
- Id_Const_SL32 = 71,
+ Id_Const_UL64 = 67,
Id_Const_Z = 72,
Id_Const_0 = 73,
Id_Const_Bit = 74,
diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads
index 649503796..da72811e0 100644
--- a/src/synth/netlists-gates.ads
+++ b/src/synth/netlists-gates.ads
@@ -144,16 +144,11 @@ package Netlists.Gates is
-- Constants are gates with only one constant output. There are multiple
-- kind of constant gates: for small width, the value is stored as a
- -- parameter, possibly signed or unsigned extended. For large width
- -- (> 128), the value is stored in a table.
+ -- parameter, possibly signed or unsigned extended.
Id_Const_UB32 : constant Module_Id := 64;
Id_Const_UL32 : constant Module_Id := 70;
- Id_Const_SB32 : constant Module_Id := 65;
Id_Const_UB64 : constant Module_Id := 66;
- Id_Const_SB64 : constant Module_Id := 67;
- Id_Const_UB128 : constant Module_Id := 68;
- Id_Const_SB128 : constant Module_Id := 69;
- Id_Const_SL32 : constant Module_Id := 71;
+ Id_Const_UL64 : constant Module_Id := 67;
Id_Const_Z : constant Module_Id := 72;
Id_Const_0 : constant Module_Id := 73;
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb
index 6fdd413a5..4d443d999 100644
--- a/src/synth/synth-expr.adb
+++ b/src/synth/synth-expr.adb
@@ -43,6 +43,10 @@ with Netlists.Builders; use Netlists.Builders;
with Netlists.Locations; use Netlists.Locations;
package body Synth.Expr is
+ -- As log2(3m) is directly referenced, the program must be linked with -lm
+ -- (math library) on unix systems.
+ pragma Linker_Options ("-lm");
+
function Synth_Name (Syn_Inst : Synth_Instance_Acc; Name : Node)
return Value_Acc;
@@ -373,7 +377,9 @@ package body Synth.Expr is
end if;
end loop;
when Iir_Kind_Choice_By_Name =>
- Pos := Natural (Get_Element_Position (Get_Name (Assoc)));
+ Pos := Natural (Get_Element_Position
+ (Get_Named_Entity
+ (Get_Choice_Name (Assoc))));
Set_Elem (Pos);
when others =>
Error_Msg_Synth
@@ -586,7 +592,8 @@ package body Synth.Expr is
case Get_Kind (Bound) is
when Iir_Kind_Range_Expression =>
return Synth_Discrete_Range_Expression (Syn_Inst, Bound);
- when Iir_Kind_Integer_Subtype_Definition =>
+ when Iir_Kind_Integer_Subtype_Definition
+ | Iir_Kind_Enumeration_Subtype_Definition =>
if Get_Type_Declarator (Bound) /= Null_Node then
-- This is a named subtype, so it has been evaluated.
return Get_Value_Type (Syn_Inst, Bound).Drange;
@@ -1394,6 +1401,8 @@ package body Synth.Expr is
return Synth_Vec_Reduce_Monadic(Id_Red_And);
when Iir_Predefined_Ieee_1164_Vector_Or_Reduce =>
return Synth_Vec_Reduce_Monadic(Id_Red_Or);
+ when Iir_Predefined_Ieee_1164_Condition_Operator =>
+ return Operand;
when others =>
Error_Msg_Synth
(+Loc,
diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb
index 1a3805c77..c36400e91 100644
--- a/src/synth/synth-stmts.adb
+++ b/src/synth/synth-stmts.adb
@@ -1019,8 +1019,6 @@ package body Synth.Stmts is
while Is_Valid (Assoc) loop
Inter := Get_Association_Interface (Assoc, Assoc_Inter);
- Synth_Declaration_Type (Subprg_Inst, Inter);
-
case Iir_Parameter_Modes (Get_Mode (Inter)) is
when Iir_In_Mode =>
case Get_Kind (Assoc) is
@@ -1230,6 +1228,8 @@ package body Synth.Stmts is
exit;
when Iir_Kind_Procedure_Call_Statement =>
Synth_Procedure_Call (Syn_Inst, Stmt);
+ when Iir_Kind_Report_Statement =>
+ null;
when others =>
Error_Kind ("synth_sequential_statements", Stmt);
end case;
diff --git a/src/vhdl/vhdl-annotations.adb b/src/vhdl/vhdl-annotations.adb
index d81e70adf..0b15f37b0 100644
--- a/src/vhdl/vhdl-annotations.adb
+++ b/src/vhdl/vhdl-annotations.adb
@@ -487,7 +487,10 @@ package body Vhdl.Annotations is
| Iir_Kind_Interface_Variable_Declaration
| Iir_Kind_Interface_Constant_Declaration
| Iir_Kind_Interface_File_Declaration =>
- Annotate_Anonymous_Type_Definition (Block_Info, Get_Type (El));
+ if Get_Subtype_Indication (El) /= Null_Iir then
+ Annotate_Anonymous_Type_Definition
+ (Block_Info, Get_Type (El));
+ end if;
when others =>
Error_Kind ("annotate_interface_list_subtype", El);
end case;
@@ -877,7 +880,8 @@ package body Vhdl.Annotations is
when Iir_Kind_Simple_Signal_Assignment_Statement
| Iir_Kind_Selected_Waveform_Assignment_Statement
| Iir_Kind_Conditional_Signal_Assignment_Statement
- | Iir_Kind_Variable_Assignment_Statement =>
+ | Iir_Kind_Variable_Assignment_Statement
+ | Iir_Kind_Conditional_Variable_Assignment_Statement =>
null;
when Iir_Kind_Procedure_Call_Statement =>
null;
diff --git a/src/vhdl/vhdl-ieee-numeric.adb b/src/vhdl/vhdl-ieee-numeric.adb
index 4a9ba8508..a1ac7927e 100644
--- a/src/vhdl/vhdl-ieee-numeric.adb
+++ b/src/vhdl/vhdl-ieee-numeric.adb
@@ -429,6 +429,36 @@ package body Vhdl.Ieee.Numeric is
raise Error;
end if;
end Handle_Resize;
+
+ procedure Handle_Std_Match
+ is
+ Predefined : Iir_Predefined_Functions;
+ begin
+ if Arg1_Kind /= Arg2_Kind or else Arg1_Sign /= Arg2_Sign then
+ raise Error;
+ end if;
+
+ if Arg1_Kind = Arg_Scal and Arg1_Sign = Type_Log then
+ Predefined := Iir_Predefined_Ieee_Numeric_Std_Match_Log;
+ elsif Arg1_Kind = Arg_Vect then
+ case Arg1_Sign is
+ when Type_Unsigned =>
+ Predefined := Iir_Predefined_Ieee_Numeric_Std_Match_Uns;
+ when Type_Signed =>
+ Predefined := Iir_Predefined_Ieee_Numeric_Std_Match_Sgn;
+ when Type_Suv =>
+ Predefined := Iir_Predefined_Ieee_Numeric_Std_Match_Suv;
+ when Type_Slv =>
+ Predefined := Iir_Predefined_Ieee_Numeric_Std_Match_Slv;
+ when Type_Log =>
+ raise Error;
+ end case;
+ else
+ raise Error;
+ end if;
+
+ Set_Implicit_Definition (Decl, Predefined);
+ end Handle_Std_Match;
begin
Decl := Get_Declaration_Chain (Pkg_Decl);
@@ -537,6 +567,8 @@ package body Vhdl.Ieee.Numeric is
Handle_To_Signed;
when Name_Resize =>
Handle_Resize;
+ when Name_Std_Match =>
+ Handle_Std_Match;
when others =>
null;
end case;
diff --git a/src/vhdl/vhdl-ieee-std_logic_1164.adb b/src/vhdl/vhdl-ieee-std_logic_1164.adb
index 14468e1c4..7ea7da787 100644
--- a/src/vhdl/vhdl-ieee-std_logic_1164.adb
+++ b/src/vhdl/vhdl-ieee-std_logic_1164.adb
@@ -250,11 +250,21 @@ package body Vhdl.Ieee.Std_Logic_1164 is
end case;
Set_Implicit_Definition (Decl, Predefined);
end;
- elsif Is_Scalar_Function (Decl)
- and then Get_Identifier (Decl) = Name_Not
- then
- Set_Implicit_Definition
- (Decl, Iir_Predefined_Ieee_1164_Scalar_Not);
+ elsif Is_Scalar_Function (Decl) then
+ declare
+ Predefined : Iir_Predefined_Functions;
+ begin
+ case Get_Identifier (Decl) is
+ when Name_Not =>
+ Predefined := Iir_Predefined_Ieee_1164_Scalar_Not;
+ when Name_Op_Condition =>
+ Predefined :=
+ Iir_Predefined_Ieee_1164_Condition_Operator;
+ when others =>
+ Predefined := Iir_Predefined_None;
+ end case;
+ Set_Implicit_Definition (Decl, Predefined);
+ end;
elsif Is_Vector_Vector_Function (Decl) then
declare
Predefined : Iir_Predefined_Functions;
diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads
index 41ef5fd9e..3a2bcb20b 100644
--- a/src/vhdl/vhdl-nodes.ads
+++ b/src/vhdl/vhdl-nodes.ads
@@ -4905,6 +4905,8 @@ package Vhdl.Nodes is
Iir_Predefined_Ieee_1164_Vector_And_Reduce,
Iir_Predefined_Ieee_1164_Vector_Or_Reduce,
+ Iir_Predefined_Ieee_1164_Condition_Operator,
+
-- Numeric_Std.
-- Abbreviations:
-- Uns: Unsigned, Sgn: Signed, Nat: Natural, Int: Integer.
@@ -5003,6 +5005,13 @@ package Vhdl.Nodes is
Iir_Predefined_Ieee_Numeric_Std_Neg_Uns,
Iir_Predefined_Ieee_Numeric_Std_Neg_Sgn,
+ -- Std_Match functions.
+ Iir_Predefined_Ieee_Numeric_Std_Match_Log,
+ Iir_Predefined_Ieee_Numeric_Std_Match_Uns,
+ Iir_Predefined_Ieee_Numeric_Std_Match_Sgn,
+ Iir_Predefined_Ieee_Numeric_Std_Match_Slv,
+ Iir_Predefined_Ieee_Numeric_Std_Match_Suv,
+
-- Math_Real
Iir_Predefined_Ieee_Math_Real_Ceil,
Iir_Predefined_Ieee_Math_Real_Log2,
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-15 19:43:58 +0000