diff options
Diffstat (limited to 'src')
| -rw-r--r-- | src/synth/synth-vhdl_eval.adb | 6 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-numeric_std_unsigned.adb | 6 | ||||
| -rw-r--r-- | src/vhdl/vhdl-nodes.ads | 7 |
3 files changed, 17 insertions, 2 deletions
diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb index 4574fa6f8..89743a5a8 100644 --- a/src/synth/synth-vhdl_eval.adb +++ b/src/synth/synth-vhdl_eval.adb @@ -2102,12 +2102,14 @@ package body Synth.Vhdl_Eval is when Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Nat_Uns | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Int - | Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Nat => + | Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Nat + | Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Suv_Nat_Nat => return Eval_To_Log_Vector (Uns64 (Read_Discrete (Param1)), Read_Discrete (Param2), Res_Typ); when Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Uns_Uns - | Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Slv => + | Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Slv + | Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Suv_Nat_Suv => return Eval_To_Log_Vector (Uns64 (Read_Discrete (Param1)), Int64 (Param2.Typ.Abound.Len), Res_Typ); diff --git a/src/vhdl/vhdl-ieee-numeric_std_unsigned.adb b/src/vhdl/vhdl-ieee-numeric_std_unsigned.adb index f8c87408b..06baad51d 100644 --- a/src/vhdl/vhdl-ieee-numeric_std_unsigned.adb +++ b/src/vhdl/vhdl-ieee-numeric_std_unsigned.adb @@ -77,6 +77,12 @@ package body Vhdl.Ieee.Numeric_Std_Unsigned is elsif Arg1_Kind = Arg_Int and Arg2_Kind = Arg_Slv then Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Slv; end if; + when Name_To_Stdulogicvector => + if Arg1_Kind = Arg_Int and Arg2_Kind = Arg_Int then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Suv_Nat_Nat; + elsif Arg1_Kind = Arg_Int and Arg2_Kind = Arg_Slv then + Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Suv_Nat_Suv; + end if; when Name_Resize => if Arg2_Kind = Arg_Int then Res := Iir_Predefined_Ieee_Numeric_Std_Unsigned_Resize_Slv_Nat; diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index c0d344dda..970063e64 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -6034,6 +6034,9 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Nat, Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Slv_Nat_Slv, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Suv_Nat_Nat, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Suv_Nat_Suv, + Iir_Predefined_Ieee_Numeric_Std_Unsigned_Resize_Slv_Nat, Iir_Predefined_Ieee_Numeric_Std_Unsigned_Resize_Slv_Slv, @@ -6041,10 +6044,14 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Numeric_Std_Unsigned_Minimum_Slv_Slv, -- Math_Real + Iir_Predefined_Ieee_Math_Real_Sign, Iir_Predefined_Ieee_Math_Real_Ceil, Iir_Predefined_Ieee_Math_Real_Floor, Iir_Predefined_Ieee_Math_Real_Round, + Iir_Predefined_Ieee_Math_Real_Trunc, + Iir_Predefined_Ieee_Math_Real_Log, Iir_Predefined_Ieee_Math_Real_Log2, + Iir_Predefined_Ieee_Math_Real_Log10, Iir_Predefined_Ieee_Math_Real_Sin, Iir_Predefined_Ieee_Math_Real_Cos, Iir_Predefined_Ieee_Math_Real_Arctan, |