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Diffstat (limited to 'testsuite/gna/issue642/ent.vhdl')
-rw-r--r-- | testsuite/gna/issue642/ent.vhdl | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/testsuite/gna/issue642/ent.vhdl b/testsuite/gna/issue642/ent.vhdl new file mode 100644 index 000000000..cae8c41cd --- /dev/null +++ b/testsuite/gna/issue642/ent.vhdl @@ -0,0 +1,17 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity test is +end entity; + +architecture a of test is + signal Combined : std_logic_vector(16 downto 0); + + signal SingleBit : std_logic; + signal Part1 : std_logic_vector(7 downto 0); + signal Part2 : std_logic_vector(7 downto 0); +begin + (Part1, Part2) <= Combined(Combined'left - 1 downto 0); -- line 14: can't match 'part1' with type std_ulogic; can't match 'part2' with type std_ulogic + (SingleBit, Part1, Part2) <= Combined; -- line 15: can't match 'part1' with type std_ulogic; can't match 'part2' with type std_ulogic +end architecture; + |