diff options
Diffstat (limited to 'testsuite/gna')
36 files changed, 752 insertions, 0 deletions
diff --git a/testsuite/gna/bug058/tb.vhdl b/testsuite/gna/bug058/tb.vhdl new file mode 100644 index 000000000..779a5d6f6 --- /dev/null +++ b/testsuite/gna/bug058/tb.vhdl @@ -0,0 +1,22 @@ +package pkg1 is + generic (type t; c : natural); + generic map (t => natural, c => 5); + + function f return natural; +end pkg1; + +package body pkg1 is + function f return natural is + variable v : t; + begin + return c; + end f; +end pkg1; + +entity tb is +end tb; + +architecture behav of tb is +begin + assert work.pkg1.f = 5; +end behav; diff --git a/testsuite/gna/bug058/tb1.vhdl b/testsuite/gna/bug058/tb1.vhdl new file mode 100644 index 000000000..1e183bec2 --- /dev/null +++ b/testsuite/gna/bug058/tb1.vhdl @@ -0,0 +1,21 @@ +package pkg1 is + generic (type t; c : t); + generic map (t => natural, c => 5); + + function f return t; +end pkg1; + +package body pkg1 is + function f return t is + begin + return c; + end f; +end pkg1; + +entity tb is +end tb; + +architecture behav of tb is +begin + assert work.pkg1.f = 5; +end behav; diff --git a/testsuite/gna/bug058/tb2.vhdl b/testsuite/gna/bug058/tb2.vhdl new file mode 100644 index 000000000..98f7bc5c1 --- /dev/null +++ b/testsuite/gna/bug058/tb2.vhdl @@ -0,0 +1,20 @@ +entity tb2 is +end tb2; + +architecture behav of tb2 is + package pkg1 is + generic (c : natural); + generic map (c => 5); + + function f return natural; + end pkg1; + + package body pkg1 is + function f return natural is + begin + return c; + end f; + end pkg1; +begin + assert pkg1.f = 5 severity failure; +end behav; diff --git a/testsuite/gna/bug058/testsuite.sh b/testsuite/gna/bug058/testsuite.sh new file mode 100755 index 000000000..737932da6 --- /dev/null +++ b/testsuite/gna/bug058/testsuite.sh @@ -0,0 +1,15 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 + +analyze tb.vhdl +elab_simulate tb + +analyze tb2.vhdl +elab_simulate tb2 + +clean + +echo "Test successful" diff --git a/testsuite/gna/bug063/dff.expected b/testsuite/gna/bug063/dff.expected new file mode 100644 index 000000000..3e8fb698b --- /dev/null +++ b/testsuite/gna/bug063/dff.expected @@ -0,0 +1,4 @@ +dff.vhdl:10:25: invalid use of UTF8 character for ' +dff.vhdl:11:23: invalid use of UTF8 character for ' +dff.vhdl:12:23: invalid use of UTF8 character for ' +dff.vhdl:12:42: invalid use of UTF8 character for ' diff --git a/testsuite/gna/bug063/dff.vhdl b/testsuite/gna/bug063/dff.vhdl new file mode 100644 index 000000000..c1c7809a9 --- /dev/null +++ b/testsuite/gna/bug063/dff.vhdl @@ -0,0 +1,17 @@ +entity DFF is + port (CLK, CLEAR, D : in bit; + Q : out bit); +end; + +architecture BEHAV of DFF is +begin +process (CLK, CLEAR) + begin + if (CLEAR = ‘1’) then + Q <= ‘0’; + elsif (CLK’event and CLK = ‘1’) then + Q <= D; + end if; + end process; +end BEHAV; + diff --git a/testsuite/gna/bug063/testsuite.sh b/testsuite/gna/bug063/testsuite.sh new file mode 100755 index 000000000..5bb108e0f --- /dev/null +++ b/testsuite/gna/bug063/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze_failure dff.vhdl 2> dff.out +diff dff.out dff.expected + +rm -f dff.out +clean + +echo "Test successful" diff --git a/testsuite/gna/bug064/repro.vhdl b/testsuite/gna/bug064/repro.vhdl new file mode 100644 index 000000000..32c94b820 --- /dev/null +++ b/testsuite/gna/bug064/repro.vhdl @@ -0,0 +1,17 @@ +package gen is + generic (type t); +end gen; + +entity e is +end entity; + +library ieee; +use ieee.std_logic_1164.all; + +architecture a of e is + subtype T_DATA is std_logic_vector(31 downto 0); + type T_DATA_VECTOR is array(natural range <>) of T_DATA; + + package pkg is new work.gen (t => t_data_vector); +begin +end architecture; diff --git a/testsuite/gna/bug064/testsuite.sh b/testsuite/gna/bug064/testsuite.sh new file mode 100755 index 000000000..b44fe1761 --- /dev/null +++ b/testsuite/gna/bug064/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze_failure repro.vhdl + +clean + +echo "Test successful" diff --git a/testsuite/gna/bug065/repro.vhdl b/testsuite/gna/bug065/repro.vhdl new file mode 100644 index 000000000..70035bbd3 --- /dev/null +++ b/testsuite/gna/bug065/repro.vhdl @@ -0,0 +1,17 @@ +package gen is + generic (type t); +end gen; + +entity e is +end entity; + +library ieee; +use ieee.std_logic_1164.all; + +architecture a of e is + subtype T_DATA is std_logic_vector(31 downto 0); + type T_DATA_VECTOR is array(natural range <>) of T_DATA; + + package pkg is new work.gen generic map (t => t_data_vector); +begin +end architecture; diff --git a/testsuite/gna/bug065/testsuite.sh b/testsuite/gna/bug065/testsuite.sh new file mode 100755 index 000000000..f4a473727 --- /dev/null +++ b/testsuite/gna/bug065/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze repro.vhdl +elab_simulate e + +clean + +echo "Test successful" diff --git a/testsuite/gna/bug066/repro.vhdl b/testsuite/gna/bug066/repro.vhdl new file mode 100644 index 000000000..3ebe995fc --- /dev/null +++ b/testsuite/gna/bug066/repro.vhdl @@ -0,0 +1,17 @@ +package foo is + procedure bar (signal a, b : in bit; signal c : out bit); + procedure bar (signal a, b, c : in bit; signal d : out bit); +end package foo; + +package body foo is + procedure bar (signal a, b : in bit; signal c : out bit) is + begin + c <= a xor b; + end procedure bar; + + procedure bar (signal a, b, c : in bit; signal d : out bit) + is + begin + d <= a xor b xor c; + end procedure bar; +end package body foo; diff --git a/testsuite/gna/bug066/testsuite.sh b/testsuite/gna/bug066/testsuite.sh new file mode 100755 index 000000000..a08478e96 --- /dev/null +++ b/testsuite/gna/bug066/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze repro.vhdl + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue107/test1.vhdl b/testsuite/gna/issue107/test1.vhdl new file mode 100644 index 000000000..4e3e74174 --- /dev/null +++ b/testsuite/gna/issue107/test1.vhdl @@ -0,0 +1,28 @@ +library ieee; + use ieee.std_logic_1164.all; + +entity ApbMasterBfmE is + generic ( + G_ADDR_WIDTH : positive := 8; --* address bus width + G_DATA_WIDTH : positive := 8; --* data bus width + G_SLAVE_COUNT : positive := 1 + ); + port ( + PRreset_n_i : in std_logic; + PClk_i : in std_logic + ); +end entity ApbMasterBfmE; + + +package MyTestPkg is new work.TestPkg generic map (G_TEST => 17); + + +architecture sim of ApbMasterBfmE is + + use work.MyTestPkg.all; + +begin + + assert false report "done" severity note; + +end architecture sim; diff --git a/testsuite/gna/issue107/testpkg.vhdl b/testsuite/gna/issue107/testpkg.vhdl new file mode 100644 index 000000000..917b08976 --- /dev/null +++ b/testsuite/gna/issue107/testpkg.vhdl @@ -0,0 +1,16 @@ +package TestPkg is + + generic ( + G_TEST : positive := 8 + ); +end package TestPkg; + + +package body TestPkg is + + procedure TestReport is + begin + report "G_TEST :" & to_string(G_TEST); + end procedure; + +end package body; diff --git a/testsuite/gna/issue107/testsuite.sh b/testsuite/gna/issue107/testsuite.sh new file mode 100755 index 000000000..4f35fc111 --- /dev/null +++ b/testsuite/gna/issue107/testsuite.sh @@ -0,0 +1,12 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 + +analyze testpkg.vhdl +analyze test1.vhdl + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue151/tb.vhdl b/testsuite/gna/issue151/tb.vhdl new file mode 100644 index 000000000..8aadd3f4b --- /dev/null +++ b/testsuite/gna/issue151/tb.vhdl @@ -0,0 +1,19 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity test is + port (in_vec : in std_logic_vector); +end entity; + +architecture rtl of test is +signal A : natural; +begin + + gen2 : if in_vec'length <= 2 generate + A <= 2; + end generate; + gen3 : if in_vec'length > 2 generate + A <= 3; + end generate; +end architecture; diff --git a/testsuite/gna/issue151/testsuite.sh b/testsuite/gna/issue151/testsuite.sh new file mode 100755 index 000000000..a77ea351b --- /dev/null +++ b/testsuite/gna/issue151/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze tb.vhdl +clean + +echo "Test successful" diff --git a/testsuite/gna/issue199/repro.vhdl b/testsuite/gna/issue199/repro.vhdl new file mode 100644 index 000000000..cc688af52 --- /dev/null +++ b/testsuite/gna/issue199/repro.vhdl @@ -0,0 +1,30 @@ +ENTITY repro IS +END repro; + +package genpkg is + generic (function match (l, R : integer) return boolean); + procedure comp (l, R : integer; res : out boolean); +end genpkg; + +package body genpkg is + procedure comp (l, R : integer; res : out boolean) is + begin + res := match (l, r); + end comp; +end genpkg; + +package my_pkg is new work.genpkg generic map (match => "="); + +use work.my_pkg.all; + +ARCHITECTURE behav OF repro IS +BEGIN + PROCESS + variable ok : boolean; + BEGIN + comp (5, 2 + 3, ok); + --ok := my_pkg.comp (5, 2 + 3); + assert ok severity error; + wait; + END PROCESS; +end behav; diff --git a/testsuite/gna/issue199/testsuite.sh b/testsuite/gna/issue199/testsuite.sh new file mode 100755 index 000000000..8d22a2073 --- /dev/null +++ b/testsuite/gna/issue199/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze repro.vhdl +elab_simulate repro + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue201/repro.vhdl b/testsuite/gna/issue201/repro.vhdl new file mode 100644 index 000000000..3f3ce9ac4 --- /dev/null +++ b/testsuite/gna/issue201/repro.vhdl @@ -0,0 +1,14 @@ +package gen is + generic (type t); +end gen; + +entity e is +end entity; + +architecture a of e is + subtype T_DATA is bit_vector(31 downto 0); + type T_DATA_VECTOR is array(natural range <>) of T_DATA; + + package pkg is new work.gen generic map (t => t_data_vector (31 downto 0)); +begin +end architecture; diff --git a/testsuite/gna/issue201/testsuite.sh b/testsuite/gna/issue201/testsuite.sh new file mode 100755 index 000000000..f4a473727 --- /dev/null +++ b/testsuite/gna/issue201/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze repro.vhdl +elab_simulate e + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue204/repro.vhdl b/testsuite/gna/issue204/repro.vhdl new file mode 100644 index 000000000..09abdbbcb --- /dev/null +++ b/testsuite/gna/issue204/repro.vhdl @@ -0,0 +1,22 @@ +package SortListGenericPkg is + generic ( + type ElementType; + type ArrayofElementType; + function array_length(A : ArrayofElementType) return natural; + function element_get(A : ArrayofElementType; index : natural) return ElementType + ); + + function inside (constant E : ElementType; constant A : in ArrayofElementType) return boolean ; +end package; + +package body SortListGenericPkg is + function inside (constant E : ElementType; constant A : in ArrayofElementType) return boolean is + begin + for i in 0 to array_length(A) - 1 loop --A'range loop + if E = element_get(A, i) then + return TRUE ; + end if ; + end loop ; + return FALSE ; + end function inside ; +end package body; diff --git a/testsuite/gna/issue204/testsuite.sh b/testsuite/gna/issue204/testsuite.sh new file mode 100755 index 000000000..7b37332aa --- /dev/null +++ b/testsuite/gna/issue204/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze repro.vhdl + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue205/repro.vhdl b/testsuite/gna/issue205/repro.vhdl new file mode 100644 index 000000000..d981e81d0 --- /dev/null +++ b/testsuite/gna/issue205/repro.vhdl @@ -0,0 +1,7 @@ +package SortListGenericPkg is + generic ( + type ElementType; + function "<"(L : ElementType; R : ElementType) return boolean; + function "<="(L : ElementType; R : ElementType) return boolean + ); +end package; diff --git a/testsuite/gna/issue205/repro1.vhdl b/testsuite/gna/issue205/repro1.vhdl new file mode 100644 index 000000000..79ccfd54f --- /dev/null +++ b/testsuite/gna/issue205/repro1.vhdl @@ -0,0 +1,33 @@ +package SortListGenericPkg is + generic ( + type ElementType; + function "<"(L : ElementType; R : ElementType) return boolean; + function "<="(L : ElementType; R : ElementType) return boolean + ); + function f (a, b : ElementType) return boolean; +end package; + +package body SortListGenericPkg is + function f (a, b : ElementType) return boolean is + begin + return a <= b; + end f; +end; + +package mysort is new work.SortListGenericPkg generic map (natural, "<", "<="); + +entity repro is +end repro; + +use work.mysort.all; +architecture behav of repro +is +begin + process + variable ok : boolean; + begin + ok := f (3, 12); + assert ok report "bad comparaison" severity failure; + wait; + end process; +end behav; diff --git a/testsuite/gna/issue205/testsuite.sh b/testsuite/gna/issue205/testsuite.sh new file mode 100755 index 000000000..eefe1e0b3 --- /dev/null +++ b/testsuite/gna/issue205/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +export GHDL_STD_FLAGS=--std=08 +analyze repro1.vhdl +elab_simulate repro + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue207/pack.vhd b/testsuite/gna/issue207/pack.vhd new file mode 100644 index 000000000..124eb9efc --- /dev/null +++ b/testsuite/gna/issue207/pack.vhd @@ -0,0 +1,91 @@ +--------------------------------------------------------------------------------
+--
+-- Package demo with two simple overloaded procedures
+--
+--------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package pack is
+
+ procedure inc(signal val:inout std_logic_vector);
+ procedure inc(signal val:inout unsigned);
+ procedure inc(signal val:inout signed);
+ procedure inc(signal val:inout integer);
+ procedure inc(variable val:inout unsigned);
+ procedure inc(variable val:inout integer);
+ procedure dec(signal val:inout std_logic_vector);
+ procedure dec(signal val:inout unsigned);
+ procedure dec(signal val:inout signed);
+ procedure dec(signal val:inout integer);
+ procedure dec(variable val:inout unsigned);
+ procedure dec(variable val:inout integer);
+
+end pack;
+
+package body pack is
+
+ procedure inc(signal val:inout std_logic_vector) is
+ begin
+ val<= std_logic_vector(unsigned(val) + 1);
+ end;
+
+ procedure inc(signal val:inout signed) is
+ begin
+ val<= val + 1;
+ end;
+
+ procedure inc(signal val:inout unsigned) is
+ begin
+ val<= val + 1;
+ end;
+
+ procedure inc(signal val:inout integer) is
+ begin
+ val<= val + 1;
+ end;
+
+ procedure inc(variable val:inout unsigned) is
+ begin
+ val := val + 1;
+ end;
+
+ procedure inc(variable val:inout integer) is
+ begin
+ val := val + 1;
+ end;
+
+ procedure dec(signal val:inout std_logic_vector) is
+ begin
+ val<= std_logic_vector(unsigned(val) - 1);
+ end;
+
+ procedure dec(signal val:inout unsigned) is
+ begin
+ val<= val - 1;
+ end;
+
+ procedure dec(signal val:inout signed) is
+ begin
+ val<= val - 1;
+ end;
+
+ procedure dec(signal val:inout integer) is
+ begin
+ val<= val - 1;
+ end;
+
+ procedure dec(variable val:inout unsigned) is
+ begin
+ val := val - 1;
+ end;
+
+ procedure dec(variable val:inout integer) is
+ begin
+ val := val - 1;
+ end;
+
+end;
+
diff --git a/testsuite/gna/issue207/pack1.vhd b/testsuite/gna/issue207/pack1.vhd new file mode 100644 index 000000000..0951b5a80 --- /dev/null +++ b/testsuite/gna/issue207/pack1.vhd @@ -0,0 +1,128 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package pack0 is + + procedure inc(signal val:inout std_logic_vector); + procedure inc(signal val:inout unsigned); + procedure inc(signal val:inout signed); + procedure inc(signal val:inout integer); + procedure dec(signal val:inout std_logic_vector); + procedure dec(signal val:inout unsigned); + procedure dec(signal val:inout signed); + procedure dec(signal val:inout integer); + +end pack0; + +package body pack0 is + + procedure inc(signal val:inout std_logic_vector) is + begin + val<= std_logic_vector(unsigned(val) + 1); + end; + + procedure inc(signal val:inout signed) is + begin + val<= val + 1; + end; + + procedure inc(signal val:inout unsigned) is + begin + val<= val + 1; + end; + + procedure inc(signal val:inout integer) is + begin + val<= val + 1; + end; + + procedure dec(signal val:inout std_logic_vector) is + begin + val<= std_logic_vector(unsigned(val) - 1); + end; + + procedure dec(signal val:inout unsigned) is + begin + val<= val - 1; + end; + + procedure dec(signal val:inout signed) is + begin + val<= val - 1; + end; + + procedure dec(signal val:inout integer) is + begin + val<= val - 1; + end; + +end; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +package pack1 is + + procedure inc(variable val:inout unsigned); + procedure inc(variable val:inout integer); + procedure dec(variable val:inout unsigned); + procedure dec(variable val:inout integer); + +end pack1; + +package body pack1 is + + procedure inc(variable val:inout unsigned) is + begin + val := val + 1; + end; + + procedure inc(variable val:inout integer) is + begin + val := val + 1; + end; + + procedure dec(variable val:inout unsigned) is + begin + val := val - 1; + end; + + procedure dec(variable val:inout integer) is + begin + val := val - 1; + end; + +end; + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use work.pack0.all; +use work.pack1.all; + +entity overload is +end entity; + +architecture foo of overload is + signal sig: unsigned ( 7 downto 0) := (others => '0'); + signal int: integer range 0 to 255; -- 'LEFT = 0 initial value +begin + process + variable isig: unsigned ( 7 downto 0) := (others => '0'); + variable iint: integer range 0 to 255; + begin + inc(sig); + inc(isig); + inc(int); + inc(iint); + wait for 0 ns; + dec(sig); + dec(isig); + dec(int); + dec(iint); + wait; + end process; + +end architecture; diff --git a/testsuite/gna/issue207/testsuite.sh b/testsuite/gna/issue207/testsuite.sh new file mode 100755 index 000000000..3bd9f00f1 --- /dev/null +++ b/testsuite/gna/issue207/testsuite.sh @@ -0,0 +1,10 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze_failure pack.vhd +analyze_failure pack1.vhd + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue209/main.vhdl b/testsuite/gna/issue209/main.vhdl new file mode 100644 index 000000000..75198235a --- /dev/null +++ b/testsuite/gna/issue209/main.vhdl @@ -0,0 +1,14 @@ +library work; + use work.all; + +package ShiftReg is + procedure main(new_sample: integer); +end package; + +package body ShiftReg is + procedure main(new_sample: integer) is + variable dummy: Util.integer_list_t(0 to 3); -- Here i use the type + begin + dummy := new_sample & dummy(0 to dummy'high-1); -- Error about missing & + end procedure; +end package body; diff --git a/testsuite/gna/issue209/main2.vhdl b/testsuite/gna/issue209/main2.vhdl new file mode 100644 index 000000000..1d8e9f321 --- /dev/null +++ b/testsuite/gna/issue209/main2.vhdl @@ -0,0 +1,17 @@ +library work; + use work.all; + +package ShiftReg is + type integer_list_t is array (natural range <>) of integer; -- notice this line + procedure main(new_sample: integer); +end package; + +package body ShiftReg is + + procedure main(new_sample: integer) is + variable dummy: integer_list_t(0 to 3); -- notice this line + begin + dummy := new_sample & dummy(0 to dummy'high-1); --no error + end procedure; + +end package body; diff --git a/testsuite/gna/issue209/testsuite.sh b/testsuite/gna/issue209/testsuite.sh new file mode 100755 index 000000000..de9d44773 --- /dev/null +++ b/testsuite/gna/issue209/testsuite.sh @@ -0,0 +1,12 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze util.vhdl +analyze_failure main.vhdl + +analyze main2.vhdl + +clean + +echo "Test successful" diff --git a/testsuite/gna/issue209/util.vhdl b/testsuite/gna/issue209/util.vhdl new file mode 100644 index 000000000..a86ceaacb --- /dev/null +++ b/testsuite/gna/issue209/util.vhdl @@ -0,0 +1,3 @@ +package Util is + type integer_list_t is array (natural range <>) of integer; +end package; diff --git a/testsuite/gna/issue212/test.vhdl b/testsuite/gna/issue212/test.vhdl new file mode 100644 index 000000000..c322888f2 --- /dev/null +++ b/testsuite/gna/issue212/test.vhdl @@ -0,0 +1,45 @@ +PACKAGE test_pkg IS + + TYPE test_record_t IS RECORD + number : integer; + END RECORD test_record_t; + + FUNCTION set_test_record_default + RETURN test_record_t; + + FUNCTION set_test_record ( + CONSTANT C_TEST : test_record_t := set_test_record_default) + RETURN test_record_t; + +END PACKAGE test_pkg; + +PACKAGE BODY test_pkg IS + + FUNCTION set_test_record_default + RETURN test_record_t IS + VARIABLE result : test_record_t; + BEGIN + result.number := 0; + RETURN result; + END set_test_record_default; + + FUNCTION set_test_record ( + CONSTANT C_TEST : test_record_t := set_test_record_default) + RETURN test_record_t IS + BEGIN + RETURN C_TEST; + END set_test_record; + +END PACKAGE BODY test_pkg; + +ENTITY test IS +END ENTITY test; + +LIBRARY work; +USE work.test_pkg.set_test_record; + +ARCHITECTURE rtl OF test IS + +BEGIN + +END ARCHITECTURE rtl; diff --git a/testsuite/gna/issue212/testsuite.sh b/testsuite/gna/issue212/testsuite.sh new file mode 100755 index 000000000..f8534f54e --- /dev/null +++ b/testsuite/gna/issue212/testsuite.sh @@ -0,0 +1,9 @@ +#! /bin/sh + +. ../../testenv.sh + +analyze test.vhdl + +clean + +echo "Test successful" |