7 files changed, 207 insertions, 0 deletions
diff --git a/testsuite/gna/issue2395/test.vhdl b/testsuite/gna/issue2395/test.vhdl
new file mode 100644
index 000000000..7b467938e
--- /dev/null
+++ b/testsuite/gna/issue2395/test.vhdl
@@ -0,0 +1,64 @@
+library ieee ;
+    use ieee.std_logic_1164.all ;
+
+package axi4s is
+
+    type axis_t is record
+        data    :   std_ulogic_vector ;
+        dest    :   std_ulogic_vector ;
+        id      :   std_ulogic_vector ;
+        strb    :   std_ulogic_vector ;
+        keep    :   std_ulogic_vector ;
+        user    :   std_ulogic_vector ;
+        last    :   std_ulogic ;
+        valid   :   std_ulogic ;
+        ready   :   std_ulogic ;
+    end record ;
+
+    type axis_array_t is array(natural range <>) of axis_t ;
+
+    package make is
+      generic (
+        DATA_BYTES  :   positive    := 4 ;
+        DEST_WIDTH  :   natural     := 0 ;
+        ID_WIDTH    :   natural     := 0 ;
+        USER_WIDTH  :   natural     := 0
+      ) ;
+
+        subtype DATA_RANGE is natural range DATA_BYTES*8-1 downto 0 ;
+        subtype DEST_RANGE is natural range DEST_WIDTH-1 downto 0 ;
+        subtype ID_RANGE   is natural range ID_WIDTH-1 downto 0 ;
+        subtype KEEP_RANGE is natural range DATA_BYTES-1 downto 0 ;
+        subtype USER_RANGE is natural range USER_WIDTH-1 downto 0 ;
+
+        subtype axis_t is axi4s.axis_t(
+            data(DATA_RANGE),
+            dest(DEST_RANGE),
+            id(ID_RANGE),
+            keep(KEEP_RANGE),
+            strb(KEEP_RANGE),
+            user(USER_RANGE)
+        ) ;
+
+    end package ;
+
+end package ;
+
+package axis32 is new work.axi4s.make ;
+
+entity test is
+  port (
+    clock   :   in  bit ;
+    reset   :   in  bit ;
+    rx      :   inout   work.axis32.axis_t ;
+    tx      :   inout   work.axi4s.axis_t(data(31 downto 0), dest(-1 downto 0), id(-1 downto 0), keep(3 downto 0), strb(-1 downto 0), user(-1 downto 0))
+  ) ;
+end entity ;
+
+architecture arch of test is
+
+begin
+
+    -- do nothing for now
+
+end architecture ;
diff --git a/testsuite/gna/issue2395/testsuite.sh b/testsuite/gna/issue2395/testsuite.sh
new file mode 100755
index 000000000..1d84c0f57
--- /dev/null
+++ b/testsuite/gna/issue2395/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze test.vhdl
+elab_simulate test
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/gna/issue2407/shift_register.vhdl b/testsuite/gna/issue2407/shift_register.vhdl
new file mode 100644
index 000000000..e96fc7cea
--- /dev/null
+++ b/testsuite/gna/issue2407/shift_register.vhdl
@@ -0,0 +1,34 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+entity shift_register is
+  generic (
+    -- number of stages
+    NUM_STAGES: natural := 11;
+    -- number of bits
+    BITS: natural := 4
+  );
+  port (
+    clk, rst: in std_logic;
+    x: in std_logic_vector (BITS - 1 downto 0);
+    y: out std_logic_vector (BITS - 1 downto 0)
+  );
+end entity;
+architecture rtl of shift_register
+is
+  type signed_array is array (natural range <>) of signed;
+  signal shift_reg: signed_array (1 to NUM_STAGES - 1)(BITS - 1 downto 0);
+begin
+  process (clk, rst)
+  begin
+    if rst
+    then
+      shift_reg <= (others => (others => '0'));
+    elsif rising_edge (clk)
+    then
+      shift_reg <= signed (x) & shift_reg (1 to NUM_STAGES - 2);
+    end if;
+  end process;
+  y <= std_logic_vector (shift_reg (NUM_STAGES - 1));
+end architecture;
+
diff --git a/testsuite/gna/issue2407/shift_register_tb.vhdl b/testsuite/gna/issue2407/shift_register_tb.vhdl
new file mode 100644
index 000000000..9c1d9c875
--- /dev/null
+++ b/testsuite/gna/issue2407/shift_register_tb.vhdl
@@ -0,0 +1,47 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.env.finish;
+entity shift_register_tb is
+end shift_register_tb;
+architecture sim of shift_register_tb
+is
+  constant clk_hz: integer := 100e6;
+  constant clk_period: time := 1 sec / clk_hz;
+  -- number of stages
+  constant NUM_STAGES: natural := 5;
+  -- number of bits
+  constant BITS: natural := 4;
+  signal clk: std_logic := '1';
+  signal rst: std_logic := '1';
+  signal x: std_logic_vector (BITS - 1 downto 0) := (others => '0');
+  signal y: std_logic_vector (BITS - 1 downto 0);
+begin
+  clk <= not clk after clk_period / 2;
+  DUT: entity work.shift_register (rtl)
+    generic map (NUM_STAGES => NUM_STAGES, BITS => BITS)
+    port map (clk => clk, rst => rst, x => x, y => y);
+  SEQUENCER_PROC: process
+  begin
+    wait for clk_period * 2;
+    rst <= '0';
+    wait for clk_period;
+    for i in - 2** (BITS - 1) to 2** (BITS - 1) - 1 loop
+      x <= std_logic_vector (to_signed (i, BITS));
+      wait for clk_period;
+    end loop;
+    wait;
+  end process;
+  CHECK_PROC: process
+  begin
+    wait on rst;
+    wait for (NUM_STAGES + 1) * clk_period;
+    for i in - 2** (BITS - 1) to 2** (BITS - 1) - 1 loop
+      assert to_integer (signed (y)) = i report "y: " & to_string (to_integer (signed (y))) & " is not equal to " & to_string (i) severity failure;
+      wait for clk_period;
+    end loop;
+    wait for clk_period;
+    finish;
+  end process;
+end architecture;
+
diff --git a/testsuite/gna/issue2407/testsuite.sh b/testsuite/gna/issue2407/testsuite.sh
new file mode 100755
index 000000000..fe0f65add
--- /dev/null
+++ b/testsuite/gna/issue2407/testsuite.sh
@@ -0,0 +1,12 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze shift_register.vhdl
+analyze shift_register_tb.vhdl
+elab_simulate shift_register_tb
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/gna/issue2410/test.vhdl b/testsuite/gna/issue2410/test.vhdl
new file mode 100644
index 000000000..280452526
--- /dev/null
+++ b/testsuite/gna/issue2410/test.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test is
+end entity test;
+architecture beh of test is
+   type    t_slv_array is array (natural range <>) of std_logic_vector;
+   subtype t_word_array is t_slv_array(open)(15 downto 0);
+
+  procedure test_proc(
+    variable sig : out t_word_array)
+  is
+    variable v_sig : t_word_array(0 to sig'length);
+  begin
+    v_sig := (others => x"AAAA");
+    sig := v_sig(1 to sig'length);
+  end procedure;
+begin
+  
+  process
+    variable v_sig : t_word_array(0 to 0);
+  begin
+    test_proc(v_sig);
+    wait;
+  end process;
+
+end architecture beh;
diff --git a/testsuite/gna/issue2410/testsuite.sh b/testsuite/gna/issue2410/testsuite.sh
new file mode 100755
index 000000000..1d84c0f57
--- /dev/null
+++ b/testsuite/gna/issue2410/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze test.vhdl
+elab_simulate test
+
+clean
+
+echo "Test successful"