diff options
Diffstat (limited to 'testsuite/pyunit/dom/examples/StopWatch')
5 files changed, 23 insertions, 6 deletions
diff --git a/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl b/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl index ef1474164..2c4a0130f 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/Debouncer.vhdl @@ -7,7 +7,7 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; -use work.Utilities_pkg.all; +context work.Utilities_ctx; entity Debouncer is diff --git a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl index f67f99c72..3755e4575 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.pkg.vhdl @@ -30,4 +30,21 @@ package StopWatch_pkg is Seg7Code : out std_logic_vector(7 downto 0) ); end component; + + component seg7_Display is + generic ( + CLOCK_PERIOD : time := 10 ns; + REFRESH_RATE : time := 200 us; + DIGITS : positive + ); + port ( + Clock : in std_logic; + + DigitValues : in T_BCD_Vector(DIGITS - 1 downto 0); + DotValues : in std_logic_vector(DIGITS - 1 downto 0) := (others => '0'); + + Seg7_Segments : out std_logic_vector(7 downto 0); + Seg7_Selects : out std_logic_vector(DIGITS - 1 downto 0) + ); + end component; end package; diff --git a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.vhdl b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.vhdl index 3d73fa0fa..87a147833 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/StopWatch.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/StopWatch.vhdl @@ -32,7 +32,7 @@ entity Stopwatch is end entity; -architecture trl of Stopwatch is +architecture rtl of Stopwatch is type T_STATE is (ST_RESET, ST_IDLE, ST_COUNTING, ST_PAUSE); signal State : T_STATE := ST_IDLE; @@ -92,7 +92,7 @@ begin end case; end process; - TimeBaseCnt: entity work.Counter + TimeBaseCnt: entity lib_Utilities.Counter generic map ( MODULO => TIMEBASE / (CLOCK_PERIOD * ite(IS_SIMULATION, 100, 1)), BITS => 0 @@ -109,7 +109,7 @@ begin Overflows(0) <= Tick; genDigits: for i in CONFIG'range generate - cnt: entity work.Counter + cnt: entity lib_Utilities.Counter generic map ( MODULO => CONFIG(i).Modulo, BITS => Digits(i)'length diff --git a/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl b/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl index da21075cf..6ed4ecaba 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/seg7_Display.vhdl @@ -79,7 +79,7 @@ begin Dot <= DotValues(to_index(Digit_Select, DotValues'high)); -- 7-segment encoder - enc: configuration seg7_Encoder + enc: component seg7_Encoder port map ( BCDValue => Digit, Dot => Dot, diff --git a/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl b/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl index 08046e2cc..d23d75b2e 100644 --- a/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl +++ b/testsuite/pyunit/dom/examples/StopWatch/toplevel.StopWatch.vhdl @@ -100,7 +100,7 @@ begin ); -- 7-segment display - display: configuration seg7_Display_cfg + display: /* configuration */ seg7_Display--_cfg generic map ( CLOCK_PERIOD => CLOCK_PERIOD, DIGITS => Digits'length |