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Diffstat (limited to 'testsuite/pyunit/dom/examples')
| -rw-r--r-- | testsuite/pyunit/dom/examples/SimpleEntity.vhdl | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/testsuite/pyunit/dom/examples/SimpleEntity.vhdl b/testsuite/pyunit/dom/examples/SimpleEntity.vhdl index bdeae47e1..8acc3ddb5 100644 --- a/testsuite/pyunit/dom/examples/SimpleEntity.vhdl +++ b/testsuite/pyunit/dom/examples/SimpleEntity.vhdl @@ -35,8 +35,10 @@ entity Counter is end entity; --- Synthesizable and simulatable variant of a generic counter. architecture rtl of Counter is + -- Synthesizable and simulatable variant of a generic counter. + + -- Internal counter value signal CounterValue : unsigned(log2(MODULO) - 1 downto 0) := (others => '0'); begin process (Clock) |