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Diffstat (limited to 'testsuite/pyunit/libghdl/DesignComment.vhdl')
| -rw-r--r-- | testsuite/pyunit/libghdl/DesignComment.vhdl | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/testsuite/pyunit/libghdl/DesignComment.vhdl b/testsuite/pyunit/libghdl/DesignComment.vhdl new file mode 100644 index 000000000..5cd555d33 --- /dev/null +++ b/testsuite/pyunit/libghdl/DesignComment.vhdl @@ -0,0 +1,14 @@ +-- No copyright for :accum: design. + +library ieee; +use ieee.std_logic_1164.all; + +entity accum is + port ( + -- :a: and :b: are the inputs of the adder. + a, b : in std_logic_vector (31 downto 0); + -- :res: is the result of the adder. + res : out std_logic_vector (31 downto 0) + ); +end accum; + |