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-rw-r--r--testsuite/pyunit/libghdl/simpleEntity.vhdl3
1 files changed, 2 insertions, 1 deletions
diff --git a/testsuite/pyunit/libghdl/simpleEntity.vhdl b/testsuite/pyunit/libghdl/simpleEntity.vhdl
index bfcb0aceb..a26a6357c 100644
--- a/testsuite/pyunit/libghdl/simpleEntity.vhdl
+++ b/testsuite/pyunit/libghdl/simpleEntity.vhdl
@@ -3,7 +3,8 @@ use ieee.numeric_std.all;
entity e1 is
generic (
- BITS : positive = 8
+ BITS : positive := 8
+ );
port (
Clock: in std_logic;
Reset: in std_logic;