diff options
Diffstat (limited to 'testsuite/pyunit/lsp/002coverage')
| -rw-r--r-- | testsuite/pyunit/lsp/002coverage/cmds.json | 471 | ||||
| -rw-r--r-- | testsuite/pyunit/lsp/002coverage/cmds.lsp | 35 | ||||
| -rw-r--r-- | testsuite/pyunit/lsp/002coverage/hdl-prj.json | 5 | ||||
| -rw-r--r-- | testsuite/pyunit/lsp/002coverage/replies.json | 627 | ||||
| -rw-r--r-- | testsuite/pyunit/lsp/002coverage/replies.ref | 33 | ||||
| -rw-r--r-- | testsuite/pyunit/lsp/002coverage/vhdl-ls.trace.in | 11 | ||||
| -rw-r--r-- | testsuite/pyunit/lsp/002coverage/vhdl-ls.trace.out | 9 |
7 files changed, 1191 insertions, 0 deletions
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"workspaceFolders": [ + { + "uri": "file:///home/tgingold/work/vhdl-language-server/tests/002coverage", + "name": "002coverage" + } + ] + } + }, + { + "jsonrpc": "2.0", + "method": "initialized", + "params": {} + }, + { + "jsonrpc": "2.0", + "method": "textDocument/didOpen", + "params": { + "textDocument": { + "uri": "file:///home/tgingold/work/vhdl-language-server/tests/files/adder.vhdl", + "languageId": "vhdl", + "version": 1, + "text": "\nentity adder is\n -- `i0`, `i1`, and the carry-in `ci` are inputs of the adder.\n -- `s` is the sum output, `co` is the carry-out.\n port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);\nend adder;\n\narchitecture rtl of adder is\nbegin\n -- This full-adder architecture contains two concurrent assignments.\n -- Compute the sum.\n s <= i0 xor i1 xor ci;\n -- Compute the carry.\n co <= (i0 and i1) or (i0 and ci) or (i1 and ci);\nend rtl;\n\n" + } + } + }, + { + "jsonrpc": "2.0", + "id": 1, + "method": "textDocument/documentSymbol", + "params": { + "textDocument": { + "uri": "file:///home/tgingold/work/vhdl-language-server/tests/files/adder.vhdl" + } + } + }, + { + "jsonrpc": "2.0", + "method": "textDocument/didOpen", + "params": { + "textDocument": { + "uri": "file:///home/tgingold/work/vhdl-language-server/tests/files/adder_tb.vhdl", + "languageId": "vhdl", + "version": 1, + "text": "\n-- A testbench has no ports.\nentity adder_tb is\nend adder_tb;\n\narchitecture behav of adder_tb is\n -- Declaration of the component that will be instantiated.\n component adder\n port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);\n end component;\n\n -- Specifies which entity is bound with the component.\n for adder_0: adder use entity work.adder;\n signal i0, i1, ci, s, co : bit;\nbegin\n -- Component instantiation.\n adder_0: adder port map (i0 => i0, i1 => i1, ci => ci,\n s => s, co => co);\n\n -- This process does the real job.\n process\n type pattern_type is record\n -- The inputs of the adder.\n i0, i1, ci : bit;\n -- The expected outputs of the adder.\n s, co : bit;\n end record;\n -- The patterns to apply.\n type pattern_array is array (natural range <>) of pattern_type;\n constant patterns : pattern_array :=\n (('0', '0', '0', '0', '0'),\n ('0', '0', '1', '1', '0'),\n ('0', '1', '0', '1', '0'),\n ('0', '1', '1', '0', '1'),\n ('1', '0', '0', '1', '0'),\n ('1', '0', '1', '0', '1'),\n ('1', '1', '0', '0', '1'),\n ('1', '1', '1', '1', '1'));\n begin\n -- Check each pattern.\n for i in patterns'range loop\n -- Set the inputs.\n i0 <= patterns(i).i0;\n i1 <= patterns(i).i1;\n ci <= patterns(i).ci;\n -- Wait for the results.\n wait for 1 ns;\n -- Check the outputs.\n assert s = patterns(i).s\n report \"bad sum value\" severity error;\n assert co = patterns(i).co\n report \"bad carry out value\" severity error;\n end loop;\n assert false report \"end of test\" severity note;\n -- Wait forever; this will finish the simulation.\n wait;\n end process;\nend behav;\n\n\n" + } + } + }, + { + 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