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-rw-r--r--testsuite/pyunit/lsp/003errors/cmds.json245
-rw-r--r--testsuite/pyunit/lsp/003errors/crash1.json229
-rw-r--r--testsuite/pyunit/lsp/003errors/crash2.json239
-rw-r--r--testsuite/pyunit/lsp/003errors/replies.json110
-rw-r--r--testsuite/pyunit/lsp/003errors/tc.vhdl12
5 files changed, 835 insertions, 0 deletions
diff --git a/testsuite/pyunit/lsp/003errors/cmds.json b/testsuite/pyunit/lsp/003errors/cmds.json
new file mode 100644
index 000000000..03d6b1e37
--- /dev/null
+++ b/testsuite/pyunit/lsp/003errors/cmds.json
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+ "text": "library ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity tb is\nend tb;\n\narchitecture behav of tb is\n signal s : std_logic_vector(7 downto 0);\nbegin\n assert s /= x\"73\";\nend behav; \n"
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diff --git a/testsuite/pyunit/lsp/003errors/crash1.json b/testsuite/pyunit/lsp/003errors/crash1.json
new file mode 100644
index 000000000..155770d78
--- /dev/null
+++ b/testsuite/pyunit/lsp/003errors/crash1.json
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+ }
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+ }
+]
diff --git a/testsuite/pyunit/lsp/003errors/crash2.json b/testsuite/pyunit/lsp/003errors/crash2.json
new file mode 100644
index 000000000..ab12ed3bf
--- /dev/null
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+ "text": "library ieee;\nuse ieee.std_logic_1164.all;\nuse ieee.std_logic_unsigned.all;\n\nentity tb is\nend tb;\n\narchitecture behav of tb is\n signal s : std_logic_vector(7 downto 0);\nbegin\n assert s != x\"73\";\n end process;\nend behav; \n"
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diff --git a/testsuite/pyunit/lsp/003errors/replies.json b/testsuite/pyunit/lsp/003errors/replies.json
new file mode 100644
index 000000000..02e9cac85
--- /dev/null
+++ b/testsuite/pyunit/lsp/003errors/replies.json
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+ "character": 9
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+ "character": 9
+ }
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+ "message": "unit \"std_logic_unsigned\" not found in library \"ieee\"",
+ "severity": 1
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+ "location": {
+ "uri": "file:///home/tgingold/work/vhdl-language-server/tests/003errors/tc.vhdl",
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diff --git a/testsuite/pyunit/lsp/003errors/tc.vhdl b/testsuite/pyunit/lsp/003errors/tc.vhdl
new file mode 100644
index 000000000..6308aeb6f
--- /dev/null
+++ b/testsuite/pyunit/lsp/003errors/tc.vhdl
@@ -0,0 +1,12 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+
+entity tb is
+end tb;
+
+architecture behav of tb is
+ signal s : std_logic_vector(7 downto 0);
+begin
+ assert s /= x"73";
+end behav;
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-27 17:22:24 +0000