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Diffstat (limited to 'testsuite/pyunit/lsp/010ls28/top.vhdl')
-rw-r--r-- | testsuite/pyunit/lsp/010ls28/top.vhdl | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/testsuite/pyunit/lsp/010ls28/top.vhdl b/testsuite/pyunit/lsp/010ls28/top.vhdl new file mode 100644 index 000000000..d371cce2e --- /dev/null +++ b/testsuite/pyunit/lsp/010ls28/top.vhdl @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity top is + port ( + clk : in std_logic; + sum : out std_logic + ); +end entity; + +architecture rtl of top is +begin + + adder : entity work.adder(comb) + port map( + a => clk, + b => '1', + o => sum, + c => open + ); + +end architecture; |