4 files changed, 117 insertions, 0 deletions
diff --git a/testsuite/pyunit/lsp/files/adder.vhdl b/testsuite/pyunit/lsp/files/adder.vhdl
new file mode 100644
index 000000000..38ff2a60f
--- /dev/null
+++ b/testsuite/pyunit/lsp/files/adder.vhdl
@@ -0,0 +1,16 @@
+
+entity adder is
+  -- `i0`, `i1`, and the carry-in `ci` are inputs of the adder.
+  -- `s` is the sum output, `co` is the carry-out.
+  port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
+end adder;
+
+architecture rtl of adder is
+begin
+  --  This full-adder architecture contains two concurrent assignments.
+  --  Compute the sum.
+  s <= i0 xor i1 xor ci;
+  --  Compute the carry.
+  co <= (i0 and i1) or (i0 and ci) or (i1 and ci);
+end rtl;
+
diff --git a/testsuite/pyunit/lsp/files/adder_tb.vhdl b/testsuite/pyunit/lsp/files/adder_tb.vhdl
new file mode 100644
index 000000000..7dd9f60b5
--- /dev/null
+++ b/testsuite/pyunit/lsp/files/adder_tb.vhdl
@@ -0,0 +1,60 @@
+
+--  A testbench has no ports.
+entity adder_tb is
+end adder_tb;
+
+architecture behav of adder_tb is
+  --  Declaration of the component that will be instantiated.
+  component adder
+    port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
+  end component;
+
+  --  Specifies which entity is bound with the component.
+  for adder_0: adder use entity work.adder;
+  signal i0, i1, ci, s, co : bit;
+begin
+  --  Component instantiation.
+  adder_0: adder port map (i0 => i0, i1 => i1, ci => ci,
+                           s => s, co => co);
+
+  --  This process does the real job.
+  process
+    type pattern_type is record
+      --  The inputs of the adder.
+      i0, i1, ci : bit;
+      --  The expected outputs of the adder.
+      s, co : bit;
+    end record;
+    --  The patterns to apply.
+    type pattern_array is array (natural range <>) of pattern_type;
+    constant patterns : pattern_array :=
+      (('0', '0', '0', '0', '0'),
+       ('0', '0', '1', '1', '0'),
+       ('0', '1', '0', '1', '0'),
+       ('0', '1', '1', '0', '1'),
+       ('1', '0', '0', '1', '0'),
+       ('1', '0', '1', '0', '1'),
+       ('1', '1', '0', '0', '1'),
+       ('1', '1', '1', '1', '1'));
+  begin
+    --  Check each pattern.
+    for i in patterns'range loop
+      --  Set the inputs.
+      i0 <= patterns(i).i0;
+      i1 <= patterns(i).i1;
+      ci <= patterns(i).ci;
+      --  Wait for the results.
+      wait for 1 ns;
+      --  Check the outputs.
+      assert s = patterns(i).s
+        report "bad sum value" severity error;
+      assert co = patterns(i).co
+        report "bad carry out value" severity error;
+    end loop;
+    assert false report "end of test" severity note;
+    --  Wait forever; this will finish the simulation.
+    wait;
+  end process;
+end behav;
+
+
diff --git a/testsuite/pyunit/lsp/files/heartbeat.vhdl b/testsuite/pyunit/lsp/files/heartbeat.vhdl
new file mode 100644
index 000000000..6dfc1a1e1
--- /dev/null
+++ b/testsuite/pyunit/lsp/files/heartbeat.vhdl
@@ -0,0 +1,22 @@
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity heartbeat is
+  port ( clk: out std_logic);
+end heartbeat;
+
+architecture behaviour of heartbeat
+is
+  constant clk_period : time := 10 ns;
+begin
+  -- Clock process definition
+  clk_process: process
+  begin
+    clk <= '0';
+    wait for clk_period/2;
+    clk <= '1';
+    wait for clk_period/2;
+  end process;
+end behaviour;
+
diff --git a/testsuite/pyunit/lsp/files/hello.vhdl b/testsuite/pyunit/lsp/files/hello.vhdl
new file mode 100644
index 000000000..f93578b4a
--- /dev/null
+++ b/testsuite/pyunit/lsp/files/hello.vhdl
@@ -0,0 +1,19 @@
+
+--  Hello world program
+use std.textio.all; -- Imports the standard textio package.
+
+--  Defines a design entity, without any ports.
+entity hello_world is
+end hello_world;
+
+architecture behaviour of hello_world is
+begin
+  process
+    variable l : line;
+  begin
+    write (l, String'("Hello world!"));
+    writeline (output, l);
+    wait;
+  end process;
+end behaviour;
+