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-rw-r--r--testsuite/synth/aggr01/tb_aggr02.vhdl25
1 files changed, 25 insertions, 0 deletions
diff --git a/testsuite/synth/aggr01/tb_aggr02.vhdl b/testsuite/synth/aggr01/tb_aggr02.vhdl
new file mode 100644
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--- /dev/null
+++ b/testsuite/synth/aggr01/tb_aggr02.vhdl
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+entity tb_aggr02 is
+end tb_aggr02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_aggr02 is
+ signal a, b : std_logic_vector(7 downto 0);
+begin
+ dut: entity work.aggr02
+ port map (a, b);
+
+ process
+ begin
+ a <= x"ff";
+ wait for 1 ns;
+ assert b = x"fe" severity failure;
+
+ a <= x"ee";
+ wait for 1 ns;
+ assert b = x"ee" severity failure;
+
+ wait;
+ end process;
+end behav;