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-rw-r--r--testsuite/synth/dispout01/tb_rec07.vhdl27
1 files changed, 27 insertions, 0 deletions
diff --git a/testsuite/synth/dispout01/tb_rec07.vhdl b/testsuite/synth/dispout01/tb_rec07.vhdl
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+++ b/testsuite/synth/dispout01/tb_rec07.vhdl
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+entity tb_rec07 is
+end tb_rec07;
+
+library ieee;
+use ieee.std_logic_1164.all;
+use work.rec07_pkg.all;
+
+architecture behav of tb_rec07 is
+ signal inp : std_logic;
+ signal r : myrec;
+begin
+ dut: entity work.rec07
+ port map (inp => inp, o => r);
+
+ process
+ begin
+ inp <= '1';
+ wait for 1 ns;
+ assert r = (a => "0001", b => '0') severity failure;
+
+ inp <= '0';
+ wait for 1 ns;
+ assert r = (a => "1000", b => '1') severity failure;
+
+ wait;
+ end process;
+end behav;