1 files changed, 24 insertions, 0 deletions
diff --git a/testsuite/synth/issue1116/ent1.vhdl b/testsuite/synth/issue1116/ent1.vhdl
new file mode 100644
index 000000000..e7621b06c
--- /dev/null
+++ b/testsuite/synth/issue1116/ent1.vhdl
@@ -0,0 +1,24 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity ent1 is
+	port (
+		clk : in std_logic;
+		i : in std_logic_vector(31 downto 0);
+		o : out std_logic_vector(7 downto 0)
+	);
+end;
+
+architecture a of ent1 is
+	function switch_endianness(x : std_logic_vector(31 downto 0)) return std_logic_vector is
+	begin
+		return x(7 downto 0) & x(15 downto 8) & x(23 downto 16) & x(31 downto 24);
+	end function;
+begin
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			o <= switch_endianness(i)(7 downto 0);
+		end if;
+	end process;
+end;