1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/synth/issue1211/repro1.vhdl b/testsuite/synth/issue1211/repro1.vhdl
new file mode 100644
index 000000000..5e2f1bf41
--- /dev/null
+++ b/testsuite/synth/issue1211/repro1.vhdl
@@ -0,0 +1,26 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity repro1 is
+	port (
+		Clock   : in std_ulogic;
+		Reset   : in std_ulogic;
+		Sig_in  : in std_ulogic;
+		Sig_out : out std_ulogic
+	);
+end entity;
+
+architecture rtl of repro1 is
+begin
+  reg: process(Clock, Reset)
+    variable pl_regs : std_ulogic;
+  begin
+    if Reset = '1' then
+      pl_regs := '0';
+    elsif rising_edge(Clock) then
+      pl_regs := Sig_in;
+    end if;
+
+    Sig_out <= pl_regs;
+  end process;
+end architecture;