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-rw-r--r--testsuite/synth/issue1253/repro2.vhdl24
1 files changed, 24 insertions, 0 deletions
diff --git a/testsuite/synth/issue1253/repro2.vhdl b/testsuite/synth/issue1253/repro2.vhdl
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+++ b/testsuite/synth/issue1253/repro2.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_arith.all;
+
+entity repro1 is
+ port(C, CLR : in std_logic;
+ Q : out std_logic_vector(3 downto 0));
+end repro1;
+
+architecture archi of repro1 is
+ signal tmp: signed(3 downto 0);
+begin
+ process (C, CLR)
+ begin
+ if (CLR='1') then
+ tmp <= "0000";
+ elsif (C'event and C='1') then
+ tmp <= 1 + tmp;
+ end if;
+ end process;
+
+ Q <= std_logic_vector(tmp);
+
+end archi;