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-rw-r--r--testsuite/synth/issue1258/ent.vhdl28
1 files changed, 28 insertions, 0 deletions
diff --git a/testsuite/synth/issue1258/ent.vhdl b/testsuite/synth/issue1258/ent.vhdl
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+++ b/testsuite/synth/issue1258/ent.vhdl
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+-- count number of '1'.
+library ieee;
+use ieee.std_logic_1164.all;
+entity ent is
+ port (
+ sel : in std_ulogic;
+ din : in std_ulogic_vector(15 downto 0);
+ dout : out std_ulogic
+ );
+end;
+
+architecture rtl of ent is
+begin
+ comb : process (sel, din)
+ variable v : std_ulogic;
+ begin
+ v := '0';
+ if sel = '1' then
+ for i in din'range loop
+ if din(i) = '0' then
+ next;
+ end if;
+ v := not v;
+ end loop;
+ end if;
+ dout <= v;
+ end process;
+end;