1 files changed, 12 insertions, 0 deletions
diff --git a/testsuite/synth/issue1272/issue.vhdl b/testsuite/synth/issue1272/issue.vhdl
new file mode 100644
index 000000000..3a232d0c9
--- /dev/null
+++ b/testsuite/synth/issue1272/issue.vhdl
@@ -0,0 +1,12 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity issue is
+    port (clk : std_logic);
+end entity issue;
+
+architecture beh of issue is
+begin
+    --psl default clock is rising_edge (clk);
+    --psl assert (always (true or true));
+end architecture;