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-rw-r--r--testsuite/synth/issue1273/assert5.vhdl24
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diff --git a/testsuite/synth/issue1273/assert5.vhdl b/testsuite/synth/issue1273/assert5.vhdl
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+++ b/testsuite/synth/issue1273/assert5.vhdl
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+library ieee;
+use ieee.std_logic_1164.all;
+
+entity assert5 is
+ port (v : std_logic_Vector (7 downto 0);
+ en : std_logic;
+ clk : std_logic;
+ rst : std_logic;
+ res : out std_logic);
+end;
+
+architecture behav of assert5 is
+begin
+ process (clk, rst)
+ begin
+ if rst = '1' then
+ res <= '0';
+ elsif rising_edge(clk) and en = '1' then
+ assert v /= x"05";
+ res <= v(0) xor v(1);
+ end if;
+ end process;
+end behav;
+