1 files changed, 14 insertions, 0 deletions
diff --git a/testsuite/synth/issue1372/issue_psl.vhdl b/testsuite/synth/issue1372/issue_psl.vhdl
new file mode 100644
index 000000000..9597ede7f
--- /dev/null
+++ b/testsuite/synth/issue1372/issue_psl.vhdl
@@ -0,0 +1,14 @@
+vunit issue_vunit (issue(psl)) {
+
+  -- All is sensitive to rising edge of clk
+  default clock is rising_edge(clk);
+
+  -- GHDL crash if condition evaluates to true
+  test_g : if true generate
+
+    -- This assertion holds
+    CHECK_0_a : assert always (a -> b);
+
+  end generate test_g;
+
+}