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Diffstat (limited to 'testsuite/synth/issue1540/ent2.vhdl')
| -rw-r--r-- | testsuite/synth/issue1540/ent2.vhdl | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/testsuite/synth/issue1540/ent2.vhdl b/testsuite/synth/issue1540/ent2.vhdl new file mode 100644 index 000000000..f3fd57f5f --- /dev/null +++ b/testsuite/synth/issue1540/ent2.vhdl @@ -0,0 +1,14 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity ent2 is + port ( + o: out bit_vector(3 downto 0) + ); +end entity; + +architecture arch of ent2 is +begin + o <= to_bitvector(std_ulogic_vector'("01LH")); +end architecture; + |