diff options
Diffstat (limited to 'testsuite/synth/issue662/psl_onehot.vhdl')
-rw-r--r-- | testsuite/synth/issue662/psl_onehot.vhdl | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/testsuite/synth/issue662/psl_onehot.vhdl b/testsuite/synth/issue662/psl_onehot.vhdl new file mode 100644 index 000000000..feaa784df --- /dev/null +++ b/testsuite/synth/issue662/psl_onehot.vhdl @@ -0,0 +1,28 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity psl_onehot is + port (clk : in std_logic; + a, b : in std_logic_vector(3 downto 0); + c : in natural range 0 to 15 + ); +end entity psl_onehot; + + +architecture psl of psl_onehot is +begin + + -- All is sensitive to rising edge of clk + default clock is rising_edge(clk); + + -- This assertion holds + ONEHOT_0_a : assert always onehot(a); + + -- This assertion fails at cycle 12 + ONEHOT_1_a : assert always onehot(b); + + -- This assertion fails at cycle 12 + ONEHOT_2_a : assert always onehot(c); + +end architecture psl; |