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Diffstat (limited to 'testsuite/synth/mem02/ram6.vhdl')
-rw-r--r-- | testsuite/synth/mem02/ram6.vhdl | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/testsuite/synth/mem02/ram6.vhdl b/testsuite/synth/mem02/ram6.vhdl new file mode 100644 index 000000000..621e7cc27 --- /dev/null +++ b/testsuite/synth/mem02/ram6.vhdl @@ -0,0 +1,25 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity ram6 is + port (val : out std_logic_vector (7 downto 0); + waddr : std_logic_vector (2 downto 0); + wdat : std_logic; + clk : std_logic); +end ram6; + +architecture behav of ram6 is + signal mem : std_logic_vector(0 to 7); +begin + process (clk) + variable ra : natural; + variable wa : natural; + begin + if rising_edge (clk) then + ra := to_integer(unsigned (waddr)); + mem(ra) <= wdat; + end if; + end process; + val <= mem; +end behav; |