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-rw-r--r--testsuite/synth/mem2d01/NOTES.txt7
-rw-r--r--testsuite/synth/mem2d01/dpram1r.vhdl26
-rw-r--r--testsuite/synth/mem2d01/dpram2r.vhdl26
-rw-r--r--testsuite/synth/mem2d01/dpram2w.vhdl26
-rw-r--r--testsuite/synth/mem2d01/memmux04.vhdl39
-rw-r--r--testsuite/synth/mem2d01/tb_dpram1r.vhdl72
-rw-r--r--testsuite/synth/mem2d01/tb_dpram2r.vhdl72
-rw-r--r--testsuite/synth/mem2d01/tb_dpram2w.vhdl92
-rw-r--r--testsuite/synth/mem2d01/tb_memmux04.vhdl83
-rwxr-xr-xtestsuite/synth/mem2d01/testsuite.sh14
10 files changed, 0 insertions, 457 deletions
diff --git a/testsuite/synth/mem2d01/NOTES.txt b/testsuite/synth/mem2d01/NOTES.txt
deleted file mode 100644
index 17ed281fb..000000000
--- a/testsuite/synth/mem2d01/NOTES.txt
+++ /dev/null
@@ -1,7 +0,0 @@
-Tests for RAMs
---------------
-
-dpram1r: Read(2d)+Write(1d), using indexes
-dpram2r: Read(2d)+Write(1d), using slices.
-dpram2w: Read(1d)+Write(2d), using slices.
-memmux04: Read(2d)+Write(1d), enable on write, intermediate variable for read.
diff --git a/testsuite/synth/mem2d01/dpram1r.vhdl b/testsuite/synth/mem2d01/dpram1r.vhdl
deleted file mode 100644
index 30c0f9f39..000000000
--- a/testsuite/synth/mem2d01/dpram1r.vhdl
+++ /dev/null
@@ -1,26 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity dpram1r is
- port (raddr : natural range 0 to 3;
- rbit : natural range 0 to 7;
- rdat : out std_logic;
- waddr : natural range 0 to 3;
- wdat : std_logic_vector (7 downto 0);
- clk : std_logic);
-end dpram1r;
-
-architecture behav of dpram1r is
- type memtype is array (0 to 3) of std_logic_vector (7 downto 0);
- signal mem : memtype;
-begin
- process (clk)
- begin
- if rising_edge (clk) then
- -- Not a memory: uses different widths.
- rdat <= mem (raddr)(rbit);
- mem (waddr) <= wdat;
- end if;
- end process;
-end behav;
diff --git a/testsuite/synth/mem2d01/dpram2r.vhdl b/testsuite/synth/mem2d01/dpram2r.vhdl
deleted file mode 100644
index 0b3c4646a..000000000
--- a/testsuite/synth/mem2d01/dpram2r.vhdl
+++ /dev/null
@@ -1,26 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity dpram2r is
- port (raddr : natural range 0 to 3;
- rnib : natural range 0 to 1;
- rdat : out std_logic_vector (3 downto 0);
- waddr : natural range 0 to 3;
- wdat : std_logic_vector (7 downto 0);
- clk : std_logic);
-end dpram2r;
-
-architecture behav of dpram2r is
- type memtype is array (0 to 3) of std_logic_vector (7 downto 0);
- signal mem : memtype;
-begin
- process (clk)
- begin
- if rising_edge (clk) then
- -- Not a memory: different widths
- rdat <= mem (raddr)(rnib * 4 + 3 downto rnib * 4);
- mem (waddr) <= wdat;
- end if;
- end process;
-end behav;
diff --git a/testsuite/synth/mem2d01/dpram2w.vhdl b/testsuite/synth/mem2d01/dpram2w.vhdl
deleted file mode 100644
index 2c412824f..000000000
--- a/testsuite/synth/mem2d01/dpram2w.vhdl
+++ /dev/null
@@ -1,26 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity dpram2w is
- port (waddr : natural range 0 to 3;
- wnib : natural range 0 to 1;
- wdat : std_logic_vector (3 downto 0);
- raddr : natural range 0 to 3;
- rdat : out std_logic_vector (7 downto 0);
- clk : std_logic);
-end dpram2w;
-
-architecture behav of dpram2w is
- type memtype is array (0 to 3) of std_logic_vector (7 downto 0);
- signal mem : memtype;
-begin
- process (clk)
- begin
- if rising_edge (clk) then
- -- Not a memory: different widths
- mem (waddr)(wnib * 4 + 3 downto wnib * 4) <= wdat;
- rdat <= mem (raddr);
- end if;
- end process;
-end behav;
diff --git a/testsuite/synth/mem2d01/memmux04.vhdl b/testsuite/synth/mem2d01/memmux04.vhdl
deleted file mode 100644
index 63f998f80..000000000
--- a/testsuite/synth/mem2d01/memmux04.vhdl
+++ /dev/null
@@ -1,39 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-entity memmux04 is
- port (
- wen : std_logic;
- waddr : std_logic_vector (3 downto 0);
- wdat : std_logic_vector (31 downto 0);
- raddr : std_logic_vector (3 downto 0);
- rsel : std_logic_vector (1 downto 0);
- rdat : out std_logic_vector(7 downto 0);
- clk : std_logic);
-end memmux04;
-
-architecture rtl of memmux04 is
-begin
- process (clk)
- is
- type mem_type is array(0 to 15) of std_logic_vector(31 downto 0);
- variable mem : mem_type;
- variable ad : natural range 0 to 15;
- variable sd : natural range 0 to 3;
- variable w : std_logic_vector (31 downto 0);
- begin
- if rising_edge(clk) then
- -- Read
- ad := to_integer(unsigned(raddr));
- w := mem (ad);
- sd := to_integer(unsigned(rsel));
- rdat <= w (sd*8 + 7 downto sd*8);
-
- ad := to_integer(unsigned(waddr));
- if wen = '1' then
- mem (ad) := wdat;
- end if;
- end if;
- end process;
-end rtl;
diff --git a/testsuite/synth/mem2d01/tb_dpram1r.vhdl b/testsuite/synth/mem2d01/tb_dpram1r.vhdl
deleted file mode 100644
index 5cfaa76ba..000000000
--- a/testsuite/synth/mem2d01/tb_dpram1r.vhdl
+++ /dev/null
@@ -1,72 +0,0 @@
-entity tb_dpram1r is
-end tb_dpram1r;
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-architecture behav of tb_dpram1r is
- signal raddr : natural range 0 to 3;
- signal rbit : natural range 0 to 7;
- signal rdat : std_logic;
- signal waddr : natural range 0 to 3;
- signal wdat : std_logic_vector(7 downto 0);
- signal clk : std_logic;
-begin
- dut: entity work.dpram1r
- port map (raddr => raddr, rbit => rbit, rdat => rdat,
- waddr => waddr, wdat => wdat,
- clk => clk);
-
- process
- procedure pulse is
- begin
- clk <= '0';
- wait for 1 ns;
- clk <= '1';
- wait for 1 ns;
- end pulse;
- begin
- raddr <= 0;
- rbit <= 0;
- waddr <= 1;
- wdat <= x"e1";
- pulse;
-
- raddr <= 1;
- rbit <= 0;
- waddr <= 0;
- wdat <= x"f0";
- pulse;
- assert rdat = '1' severity failure;
-
- raddr <= 1;
- rbit <= 1;
- waddr <= 2;
- wdat <= x"d2";
- pulse;
- assert rdat = '0' severity failure;
-
- raddr <= 1;
- rbit <= 7;
- waddr <= 3;
- wdat <= x"c3";
- pulse;
- assert rdat = '1' severity failure;
-
- raddr <= 3;
- rbit <= 7;
- waddr <= 0;
- wdat <= x"f0";
- pulse;
- assert rdat = '1' severity failure;
-
- raddr <= 3;
- rbit <= 5;
- waddr <= 0;
- wdat <= x"f0";
- pulse;
- assert rdat = '0' severity failure;
-
- wait;
- end process;
-end behav;
diff --git a/testsuite/synth/mem2d01/tb_dpram2r.vhdl b/testsuite/synth/mem2d01/tb_dpram2r.vhdl
deleted file mode 100644
index 854e5662a..000000000
--- a/testsuite/synth/mem2d01/tb_dpram2r.vhdl
+++ /dev/null
@@ -1,72 +0,0 @@
-entity tb_dpram2r is
-end tb_dpram2r;
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-architecture behav of tb_dpram2r is
- signal raddr : natural range 0 to 3;
- signal rnib : natural range 0 to 1;
- signal rdat : std_logic_vector (3 downto 0);
- signal waddr : natural range 0 to 3;
- signal wdat : std_logic_vector(7 downto 0);
- signal clk : std_logic;
-begin
- dut: entity work.dpram2r
- port map (raddr => raddr, rnib => rnib, rdat => rdat,
- waddr => waddr, wdat => wdat,
- clk => clk);
-
- process
- procedure pulse is
- begin
- clk <= '0';
- wait for 1 ns;
- clk <= '1';
- wait for 1 ns;
- end pulse;
- begin
- raddr <= 0;
- rnib <= 0;
- waddr <= 1;
- wdat <= x"e1";
- pulse;
-
- raddr <= 1;
- rnib <= 0;
- waddr <= 0;
- wdat <= x"f0";
- pulse;
- assert rdat = x"1" severity failure;
-
- raddr <= 1;
- rnib <= 1;
- waddr <= 2;
- wdat <= x"d2";
- pulse;
- assert rdat = x"e" severity failure;
-
- raddr <= 2;
- rnib <= 1;
- waddr <= 3;
- wdat <= x"c3";
- pulse;
- assert rdat = x"d" severity failure;
-
- raddr <= 3;
- rnib <= 0;
- waddr <= 0;
- wdat <= x"f0";
- pulse;
- assert rdat = x"3" severity failure;
-
- raddr <= 3;
- rnib <= 1;
- waddr <= 0;
- wdat <= x"f0";
- pulse;
- assert rdat = x"c" severity failure;
-
- wait;
- end process;
-end behav;
diff --git a/testsuite/synth/mem2d01/tb_dpram2w.vhdl b/testsuite/synth/mem2d01/tb_dpram2w.vhdl
deleted file mode 100644
index 80850d92f..000000000
--- a/testsuite/synth/mem2d01/tb_dpram2w.vhdl
+++ /dev/null
@@ -1,92 +0,0 @@
-entity tb_dpram2w is
-end tb_dpram2w;
-
-library ieee;
-use ieee.std_logic_1164.all;
-
-architecture behav of tb_dpram2w is
- signal waddr : natural range 0 to 3;
- signal wnib : natural range 0 to 1;
- signal wdat : std_logic_vector (3 downto 0);
- signal raddr : natural range 0 to 3;
- signal rdat : std_logic_vector(7 downto 0);
- signal clk : std_logic;
-begin
- dut: entity work.dpram2w
- port map (waddr => waddr, wnib => wnib, wdat => wdat,
- raddr => raddr, rdat => rdat,
- clk => clk);
-
- process
- procedure pulse is
- begin
- clk <= '0';
- wait for 1 ns;
- clk <= '1';
- wait for 1 ns;
- end pulse;
- begin
- waddr <= 0;
- wnib <= 0;
- wdat <= x"0";
- raddr <= 1;
- pulse;
-
- waddr <= 0;
- wnib <= 1;
- wdat <= x"f";
- raddr <= 1;
- pulse;
-
- waddr <= 1;
- wnib <= 1;
- wdat <= x"e";
- raddr <= 0;
- pulse;
- assert rdat = x"f0" severity failure;
-
- waddr <= 1;
- wnib <= 0;
- wdat <= x"1";
- raddr <= 0;
- pulse;
- assert rdat = x"f0" severity failure;
-
- waddr <= 3;
- wnib <= 0;
- wdat <= x"3";
- raddr <= 1;
- pulse;
- assert rdat = x"e1" severity failure;
-
- waddr <= 3;
- wnib <= 1;
- wdat <= x"c";
- raddr <= 1;
- pulse;
- assert rdat = x"e1" severity failure;
-
- waddr <= 2;
- wnib <= 1;
- wdat <= x"d";
- raddr <= 3;
- pulse;
- assert rdat = x"c3" severity failure;
-
- waddr <= 2;
- wnib <= 0;
- wdat <= x"2";
- raddr <= 3;
- pulse;
- assert rdat = x"c3" severity failure;
-
- waddr <= 1;
- wnib <= 0;
- wdat <= x"1";
- raddr <= 2;
- pulse;
- assert rdat = x"d2" severity failure;
-
- wait;
- end process;
-end behav;
diff --git a/testsuite/synth/mem2d01/tb_memmux04.vhdl b/testsuite/synth/mem2d01/tb_memmux04.vhdl
deleted file mode 100644
index 276de2460..000000000
--- a/testsuite/synth/mem2d01/tb_memmux04.vhdl
+++ /dev/null
@@ -1,83 +0,0 @@
-entity tb_memmux04 is
-end tb_memmux04;
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.numeric_std.all;
-
-architecture behav of tb_memmux04 is
- signal wen : std_logic;
- signal waddr : std_logic_vector (3 downto 0);
- signal wdat : std_logic_vector (31 downto 0);
- signal raddr : std_logic_vector (3 downto 0);
- signal rsel : std_logic_vector (1 downto 0);
- signal rdat : std_logic_vector (7 downto 0);
- signal clk : std_logic;
-begin
- dut : entity work.memmux04
- port map (
- wen => wen,
- waddr => waddr,
- wdat => wdat,
- raddr => raddr,
- rsel => rsel,
- rdat => rdat,
- clk => clk);
-
- process
- procedure pulse is
- begin
- clk <= '0';
- wait for 1 ns;
- clk <= '1';
- wait for 1 ns;
- end pulse;
-
- variable v : std_logic_vector(3 downto 0);
- variable s : std_logic_vector(1 downto 0);
- begin
- wen <= '1';
- waddr <= x"0";
- wdat <= x"0123_5670";
- pulse;
-
- wen <= '1';
- waddr <= x"1";
- wdat <= x"1234_6781";
- raddr <= x"0";
- rsel <= "00";
- pulse;
- assert rdat = x"70" severity failure;
-
- -- Fill the memory.
- for i in 0 to 15 loop
- wen <= '1';
- v := std_logic_vector (to_unsigned (i, 4));
- waddr <= v;
- wdat (3 downto 0) <= v;
- wdat (7 downto 4) <= x"0";
- wdat (11 downto 8) <= v;
- wdat (15 downto 12) <= x"1";
- wdat (19 downto 16) <= v;
- wdat (23 downto 20) <= x"2";
- wdat (27 downto 24) <= v;
- wdat (31 downto 28) <= x"3";
- pulse;
- end loop;
-
- -- Check the memory.
- wen <= '0';
- for i in 0 to 15 loop
- v := std_logic_vector (to_unsigned (i, 4));
- raddr <= v;
- for j in 0 to 3 loop
- s := std_logic_vector (to_unsigned (j, 2));
- rsel <= s;
- pulse;
- assert rdat (3 downto 0) = v severity failure;
- assert rdat (5 downto 4) = s severity failure;
- end loop;
- end loop;
- wait;
- end process;
-end behav;
diff --git a/testsuite/synth/mem2d01/testsuite.sh b/testsuite/synth/mem2d01/testsuite.sh
deleted file mode 100755
index 1c7c45546..000000000
--- a/testsuite/synth/mem2d01/testsuite.sh
+++ /dev/null
@@ -1,14 +0,0 @@
-#! /bin/sh
-
-. ../../testenv.sh
-
-for t in memmux04; do
- synth_tb $t 2> $t.log
- grep "found R" $t.log
-done
-
-for t in dpram1r dpram2r dpram2w; do
- synth_tb $t 2> $t.log
-done
-
-echo "Test successful"
generated by cgit v1.2.3 (git 2.25.1) at 2025-04-04 15:12:21 +0000