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-rw-r--r--testsuite/synth/ret01/tb_ret01.vhdl26
1 files changed, 26 insertions, 0 deletions
diff --git a/testsuite/synth/ret01/tb_ret01.vhdl b/testsuite/synth/ret01/tb_ret01.vhdl
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+++ b/testsuite/synth/ret01/tb_ret01.vhdl
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+entity tb_ret01 is
+end tb_ret01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_ret01 is
+ signal d : std_logic_vector (7 downto 0);
+ signal r : integer;
+begin
+ dut: entity work.ret01
+ port map (d, r);
+
+ process
+ begin
+ d <= x"01";
+ wait for 1 ns;
+ assert r = 1 severity failure;
+
+ d <= x"f1";
+ wait for 1 ns;
+ assert r = -1 severity failure;
+
+ wait;
+ end process;
+end behav;