6 files changed, 169 insertions, 0 deletions
diff --git a/testsuite/synth/issue2109/bug.vhdl b/testsuite/synth/issue2109/bug.vhdl
new file mode 100644
index 000000000..c514c6f99
--- /dev/null
+++ b/testsuite/synth/issue2109/bug.vhdl
@@ -0,0 +1,17 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity bug is
+generic(
+    tmp : std_ulogic_vector(0 downto 1) := ""
+);
+port(
+    val : out std_ulogic_vector(0 downto 1)
+);
+end entity;
+
+architecture rtl of bug is
+begin
+   val <= tmp;
+end architecture;
diff --git a/testsuite/synth/issue2109/testsuite.sh b/testsuite/synth/issue2109/testsuite.sh
new file mode 100755
index 000000000..1361b7a0a
--- /dev/null
+++ b/testsuite/synth/issue2109/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth --out=verilog bug.vhdl -e > syn_bug.v
+
+if grep val syn_bug.v; then
+  exit 1
+fi
+
+echo "Test successful"
diff --git a/testsuite/synth/issue2113/a.vhdl b/testsuite/synth/issue2113/a.vhdl
new file mode 100644
index 000000000..82f8039cd
--- /dev/null
+++ b/testsuite/synth/issue2113/a.vhdl
@@ -0,0 +1,59 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity a is
+	port(
+		irq : out std_ulogic
+	);
+end a;
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+entity b is
+	generic(
+		NUM_CHANNELS : positive := 4
+	);
+	port(
+		src_channel :  in integer range 0 to NUM_CHANNELS-1;
+		src_valid :  in std_ulogic;
+		src_ready : out std_ulogic
+	);
+end b;
+
+architecture struct of a is
+
+	signal src_valid       : std_ulogic;
+	signal src_ready       : std_ulogic;
+begin
+	u0 : entity work.b
+	generic map(
+		NUM_CHANNELS => 1
+	)
+	port map(
+		src_channel => 0,
+		src_valid   => src_valid,
+		src_ready   => src_ready
+	);
+end architecture;
+
+architecture behav of b is
+begin
+	process(all)
+		variable ready         : std_ulogic;
+		variable channel_ready : std_ulogic;
+	begin
+		ready := '1';
+		for i in 0 to NUM_CHANNELS-1 loop
+			if i = src_channel and src_valid = '1' then
+				channel_ready := '0';
+			else
+				channel_ready := '1';
+			end if;
+			ready := ready and channel_ready;
+		end loop;
+
+		src_ready <= ready;
+	end process;
+
+end architecture;
diff --git a/testsuite/synth/issue2113/testsuite.sh b/testsuite/synth/issue2113/testsuite.sh
new file mode 100755
index 000000000..9ab046cc4
--- /dev/null
+++ b/testsuite/synth/issue2113/testsuite.sh
@@ -0,0 +1,15 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+synth --out=verilog -Wno-nowrite a.vhdl -e > syn_a.v
+
+if grep channel syn_a.v; then
+  exit 1
+fi
+if grep "0'" syn_a.v; then
+  exit 1;
+fi
+
+echo "Test successful"
diff --git a/testsuite/synth/issue2119/test.vhdl b/testsuite/synth/issue2119/test.vhdl
new file mode 100644
index 000000000..755ea5ed8
--- /dev/null
+++ b/testsuite/synth/issue2119/test.vhdl
@@ -0,0 +1,58 @@
+-- Title      : Testcase for unbounded records
+-------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+package test_pkg is
+  type test_rec is record
+    vec_bound   : std_logic_vector(7 downto 0);
+    vec_unbound : std_logic_vector;
+    single_bit  : std_logic;
+  end record test_rec;
+end test_pkg;
+
+------------------------------------------------------------------------------------------------------------------------------------------------------
+-- Inner module
+------------------------------------------------------------------------------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+
+use work.test_pkg.all;
+
+entity test_impl is
+
+  port (
+    clk : in std_logic;
+    rec_out : out test_rec
+    );
+
+end entity test_impl;
+architecture str of test_impl is
+begin  -- architecture str
+end architecture str;
+
+------------------------------------------------------------------------------------------------------------------------------------------------------
+-- Outer Wrapper
+------------------------------------------------------------------------------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use work.test_pkg.all;
+entity test is
+
+  generic (
+    unbound_len : natural := 10
+    );
+  port (
+    clk     : in  std_logic;
+    rec_out : out test_rec(vec_unbound(unbound_len-1 downto 0)));
+end entity test;
+
+architecture str of test is
+
+begin  -- architecture str
+  test_impl_1: entity work.test_impl
+    port map (
+      clk     => clk,                   -- [in  std_logic]
+      rec_out => rec_out);              -- [out test_rec]
+end architecture str;
diff --git a/testsuite/synth/issue2119/testsuite.sh b/testsuite/synth/issue2119/testsuite.sh
new file mode 100755
index 000000000..75ca5f68d
--- /dev/null
+++ b/testsuite/synth/issue2119/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+
+synth_only test
+
+echo "Test successful"