3 files changed, 50 insertions, 0 deletions
diff --git a/testsuite/synth/range01/revrng01.vhdl b/testsuite/synth/range01/revrng01.vhdl
new file mode 100644
index 000000000..865d1dab8
--- /dev/null
+++ b/testsuite/synth/range01/revrng01.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity revrng01 is
+  port (a : std_logic_vector (7 downto 0);
+        o : out std_logic_vector (7 downto 0));
+end revrng01;
+
+architecture behav of revrng01 is
+  function rev (v : std_logic_vector) return std_logic_vector
+  is
+    variable temp : std_logic_vector(v'reverse_range);
+  begin
+    for i in v'range loop
+      temp (i) := v (i);
+    end loop;
+    return temp;
+  end rev;
+begin
+  o <= rev (a);
+end behav;
diff --git a/testsuite/synth/range01/tb_revrng01.vhdl b/testsuite/synth/range01/tb_revrng01.vhdl
new file mode 100644
index 000000000..8e29558ac
--- /dev/null
+++ b/testsuite/synth/range01/tb_revrng01.vhdl
@@ -0,0 +1,20 @@
+entity tb_revrng01 is
+end tb_revrng01;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_revrng01 is
+  signal a, z : std_logic_vector (7 downto 0);
+begin
+  dut: entity work.revrng01
+    port map (a, z);
+
+  process
+  begin
+    a <= x"a1";
+    wait for 1 ns;
+    assert z = x"85" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/range01/testsuite.sh b/testsuite/synth/range01/testsuite.sh
new file mode 100755
index 000000000..39bcc47e2
--- /dev/null
+++ b/testsuite/synth/range01/testsuite.sh
@@ -0,0 +1,9 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+for t in revrng01; do
+    synth_tb $t
+done
+
+echo "Test successful"