diff options
Diffstat (limited to 'testsuite/synth')
-rw-r--r-- | testsuite/synth/issue1372/issue.vhdl | 30 | ||||
-rw-r--r-- | testsuite/synth/issue1372/issue_psl.vhdl | 14 | ||||
-rwxr-xr-x | testsuite/synth/issue1372/testsuite.sh | 8 |
3 files changed, 52 insertions, 0 deletions
diff --git a/testsuite/synth/issue1372/issue.vhdl b/testsuite/synth/issue1372/issue.vhdl new file mode 100644 index 000000000..b44055743 --- /dev/null +++ b/testsuite/synth/issue1372/issue.vhdl @@ -0,0 +1,30 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + + +entity issue is + port ( + clk : in std_logic + ); +end entity issue; + + +architecture psl of issue is + + component sequencer is + generic ( + seq : string + ); + port ( + clk : in std_logic; + data : out std_logic + ); + end component sequencer; + + signal a, b : std_logic := '1'; + +begin + + +end architecture psl; diff --git a/testsuite/synth/issue1372/issue_psl.vhdl b/testsuite/synth/issue1372/issue_psl.vhdl new file mode 100644 index 000000000..9597ede7f --- /dev/null +++ b/testsuite/synth/issue1372/issue_psl.vhdl @@ -0,0 +1,14 @@ +vunit issue_vunit (issue(psl)) { + + -- All is sensitive to rising edge of clk + default clock is rising_edge(clk); + + -- GHDL crash if condition evaluates to true + test_g : if true generate + + -- This assertion holds + CHECK_0_a : assert always (a -> b); + + end generate test_g; + +} diff --git a/testsuite/synth/issue1372/testsuite.sh b/testsuite/synth/issue1372/testsuite.sh new file mode 100755 index 000000000..579406680 --- /dev/null +++ b/testsuite/synth/issue1372/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +synth issue.vhdl issue_psl.vhdl -e > syn_issue.vhdl + +echo "Test successful" |