diff options
Diffstat (limited to 'testsuite/synth')
| -rw-r--r-- | testsuite/synth/issue1079/tb_test2.vhdl | 58 | ||||
| -rw-r--r-- | testsuite/synth/issue1079/tb_test2n.vhdl | 53 | ||||
| -rw-r--r-- | testsuite/synth/issue1079/test2.vhdl | 41 | ||||
| -rw-r--r-- | testsuite/synth/issue1079/test2n.vhdl | 38 | ||||
| -rwxr-xr-x | testsuite/synth/issue1079/testsuite.sh | 3 | ||||
| -rw-r--r-- | testsuite/synth/issue2408/bug.vhdl | 39 | ||||
| -rwxr-xr-x | testsuite/synth/issue2408/testsuite.sh | 8 | ||||
| -rw-r--r-- | testsuite/synth/synth183/test.vhdl | 45 | ||||
| -rwxr-xr-x | testsuite/synth/synth183/testsuite.sh | 11 |
9 files changed, 296 insertions, 0 deletions
diff --git a/testsuite/synth/issue1079/tb_test2.vhdl b/testsuite/synth/issue1079/tb_test2.vhdl new file mode 100644 index 000000000..27f6037b0 --- /dev/null +++ b/testsuite/synth/issue1079/tb_test2.vhdl @@ -0,0 +1,58 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity tb_test2 is +end; + +architecture behav of tb_test2 is + signal clk : std_logic; + signal rd_en : std_logic; + signal rd_addr : std_logic_vector(7 downto 0); + signal rd_data : std_logic_vector(63 downto 0); + signal wr_en : std_logic; + signal wr_sel : std_logic_vector(7 downto 0); + signal wr_addr : std_logic_vector(7 downto 0); + signal wr_data : std_logic_vector(63 downto 0); +begin + inst_test2: entity work.test2 + port map ( + clk => clk, + rd_en => rd_en, + rd_addr => rd_addr, + rd_data => rd_data, + wr_en => wr_en, + wr_sel => wr_sel, + wr_addr => wr_addr, + wr_data => wr_data); + + process + procedure pulse is + begin + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + end pulse; + begin + rd_en <= '0'; + wr_en <= '0'; + wr_sel <= x"ff"; + pulse; + + wr_en <= '1'; + wr_addr <= x"01"; + wr_data <= x"01_12_34_56_78_9a_bc_de"; + pulse; + + wr_en <= '1'; + wr_addr <= x"02"; + wr_data <= x"02_12_34_56_78_9a_bc_de"; + + rd_en <= '1'; + rd_addr <= x"01"; + pulse; + + assert rd_data = x"01_12_34_56_78_9a_bc_de"; + wait; + end process; +end behav; diff --git a/testsuite/synth/issue1079/tb_test2n.vhdl b/testsuite/synth/issue1079/tb_test2n.vhdl new file mode 100644 index 000000000..90f975f1c --- /dev/null +++ b/testsuite/synth/issue1079/tb_test2n.vhdl @@ -0,0 +1,53 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity tb_test2n is +end; + +architecture behav of tb_test2n is + signal clk : std_logic; + signal rd_addr : std_logic_vector(7 downto 0); + signal rd_data : std_logic_vector(63 downto 0); + signal en : std_logic; + signal wr_sel : std_logic_vector(7 downto 0); + signal wr_addr : std_logic_vector(7 downto 0); + signal wr_data : std_logic_vector(63 downto 0); +begin + inst_test2n: entity work.test2n + port map ( + clk => clk, + en => en, + rd_addr => rd_addr, + rd_data => rd_data, + wr_sel => wr_sel, + wr_addr => wr_addr, + wr_data => wr_data); + + process + procedure pulse is + begin + clk <= '0'; + wait for 5 ns; + clk <= '1'; + wait for 5 ns; + end pulse; + begin + en <= '0'; + wr_sel <= x"ff"; + pulse; + + en <= '1'; + wr_addr <= x"01"; + wr_data <= x"01_12_34_56_78_9a_bc_de"; + pulse; + + wr_addr <= x"02"; + wr_data <= x"02_12_34_56_78_9a_bc_de"; + + rd_addr <= x"01"; + pulse; + + assert rd_data = x"01_12_34_56_78_9a_bc_de"; + wait; + end process; +end behav; diff --git a/testsuite/synth/issue1079/test2.vhdl b/testsuite/synth/issue1079/test2.vhdl new file mode 100644 index 000000000..a3234e0d9 --- /dev/null +++ b/testsuite/synth/issue1079/test2.vhdl @@ -0,0 +1,41 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity test2 is + port( + clk : in std_logic; + + rd_en : in std_logic; + rd_addr : in std_logic_vector(7 downto 0); + rd_data : out std_logic_vector(63 downto 0); + + wr_en : in std_logic; + wr_sel : in std_logic_vector(7 downto 0); + wr_addr : in std_logic_vector(7 downto 0); + wr_data : in std_logic_vector(63 downto 0) + ); +end test2; + +architecture rtl of test2 is + constant SIZE : integer := 2**8; + type ram_type is array (0 to SIZE - 1) of std_logic_vector(63 downto 0); + signal ram : ram_type; + signal rd_data0 : std_logic_vector(63 downto 0); +begin + process(clk) + variable widx : integer range 0 to SIZE - 1; + begin + if rising_edge(clk) then + if wr_en = '1' then + widx := to_integer(unsigned(wr_addr)); + ram(widx) <= wr_data; + end if; + if rd_en = '1' then + rd_data0 <= ram(to_integer(unsigned(rd_addr))); + end if; + end if; + end process; + + rd_data <= rd_data0; +end; diff --git a/testsuite/synth/issue1079/test2n.vhdl b/testsuite/synth/issue1079/test2n.vhdl new file mode 100644 index 000000000..f1890825d --- /dev/null +++ b/testsuite/synth/issue1079/test2n.vhdl @@ -0,0 +1,38 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity test2n is + port( + clk : in std_logic; + en : in std_logic; + + rd_addr : in std_logic_vector(7 downto 0); + rd_data : out std_logic_vector(63 downto 0); + + wr_sel : in std_logic_vector(7 downto 0); + wr_addr : in std_logic_vector(7 downto 0); + wr_data : in std_logic_vector(63 downto 0) + ); +end test2n; + +architecture rtl of test2n is + constant SIZE : integer := 2**8; + type ram_type is array (0 to SIZE - 1) of std_logic_vector(63 downto 0); + signal ram : ram_type; + signal rd_data0 : std_logic_vector(63 downto 0); +begin + process(clk) + variable widx : integer range 0 to SIZE - 1; + begin + if rising_edge(clk) then + if en /= '0' then + widx := to_integer(unsigned(wr_addr)); + ram(widx) <= wr_data; + rd_data0 <= ram(to_integer(unsigned(rd_addr))); + end if; + end if; + end process; + + rd_data <= rd_data0; +end; diff --git a/testsuite/synth/issue1079/testsuite.sh b/testsuite/synth/issue1079/testsuite.sh index 875f6aa57..4c17ce169 100755 --- a/testsuite/synth/issue1079/testsuite.sh +++ b/testsuite/synth/issue1079/testsuite.sh @@ -5,4 +5,7 @@ synth --out=raw test.vhdl -e > syn_test.raw grep -q mem_rd_sync syn_test.raw +synth_tb test2 +synth_tb test2n + echo "Test successful" diff --git a/testsuite/synth/issue2408/bug.vhdl b/testsuite/synth/issue2408/bug.vhdl new file mode 100644 index 000000000..179b30298 --- /dev/null +++ b/testsuite/synth/issue2408/bug.vhdl @@ -0,0 +1,39 @@ +library IEEE; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_arith.all; + +entity bug is + generic( + LEN : positive := 32; + POS : natural := 10 + ); + port( + output : out signed(LEN-1 downto 0) + ); + + function GET_NUM_FUNC(n : natural) return integer is + variable result :integer; + begin + case n is + when 0 => result := 16#010020#; + when 1 => result := 16#020D30#; + when 2 => result := 16#00FC1#; + when 3 => result := 16#05010#; + when 4 => result := 16#02800#; + when 5 => result := 16#01400#; + when 6 => result := 16#002F#; + when 7 => result := 16#0508#; + when 8 => result := 16#0200#; + when 9 => result := 16#0100#; + when 10 => result := 16#0A0#; + when others => result := 16#0#; + end case; + return result; + end GET_NUM_FUNC; + +end bug; + +architecture behav of bug is +begin + output <= conv_signed(GET_NUM_FUNC(POS), LEN); +end architecture; diff --git a/testsuite/synth/issue2408/testsuite.sh b/testsuite/synth/issue2408/testsuite.sh new file mode 100755 index 000000000..7de7b802c --- /dev/null +++ b/testsuite/synth/issue2408/testsuite.sh @@ -0,0 +1,8 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=-fsynopsys +synth_only bug + +echo "Test successful" diff --git a/testsuite/synth/synth183/test.vhdl b/testsuite/synth/synth183/test.vhdl new file mode 100644 index 000000000..84fc93639 --- /dev/null +++ b/testsuite/synth/synth183/test.vhdl @@ -0,0 +1,45 @@ +library ieee;
+ use ieee.std_logic_1164.all;
+
+entity test is
+ generic (
+ BAUD_MULT : positive := 16
+ );
+ port (
+ clk, rst : in std_logic;
+
+ brk : out std_logic;
+ rx : in std_logic
+ );
+end test;
+
+architecture behavioral of test is
+
+ signal rx_buf : std_logic := '1';
+ signal break : std_logic := '0';
+
+begin
+
+ BREAK_DETECTOR: process (clk, rst) is
+ constant BREAK_CNT : positive := BAUD_MULT * 11;
+ variable count : natural range 0 to BREAK_CNT + 1 := 0;
+ begin
+ if (rising_edge(clk)) then
+ rx_buf <= rx;
+ -- Add to counter if '0', but halt count when break detected
+ count := (count + 1) when not(rx_buf or break);
+ -- Reset counter if '1'
+ count := 0 when rx_buf;
+
+ break <= '0' when (count < BREAK_CNT) else '1';
+
+ if (rst = '1') then
+ count := 0;
+ break <= '0';
+ end if;
+ end if;
+ end process;
+
+ brk <= break;
+
+end behavioral;
\ No newline at end of file diff --git a/testsuite/synth/synth183/testsuite.sh b/testsuite/synth/synth183/testsuite.sh new file mode 100755 index 000000000..eb1ca0714 --- /dev/null +++ b/testsuite/synth/synth183/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 + +synth_analyze test + +clean + +echo "Test successful" |