3 files changed, 52 insertions, 1 deletions
diff --git a/testsuite/synth/func01/func07.vhdl b/testsuite/synth/func01/func07.vhdl
new file mode 100644
index 000000000..7615ad71f
--- /dev/null
+++ b/testsuite/synth/func01/func07.vhdl
@@ -0,0 +1,22 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity func07 is
+  port (v : std_ulogic_vector (15 downto 8);
+        r : out std_ulogic_vector (7 downto 0));
+end func07;
+
+architecture behav of func07 is
+  function cnt (val: std_ulogic_vector(7 downto 0)) return std_ulogic_vector is
+    variable ret: unsigned(3 downto 0) := (others => '0');
+  begin
+    for i in val'range loop
+      ret := ret + ("000" & val(i));
+    end loop;
+
+    return std_ulogic_vector(resize(ret, val'length));
+  end;
+begin
+  r <= cnt (v);
+end behav;
diff --git a/testsuite/synth/func01/tb_func07.vhdl b/testsuite/synth/func01/tb_func07.vhdl
new file mode 100644
index 000000000..d383222a0
--- /dev/null
+++ b/testsuite/synth/func01/tb_func07.vhdl
@@ -0,0 +1,29 @@
+entity tb_func07 is
+end tb_func07;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_func07 is
+  signal v, r : std_ulogic_vector(7 downto 0);
+begin
+  dut: entity work.func07
+    port map (v, r);
+
+  process
+  begin
+    v <= "00000000";
+    wait for 1 ns;
+    assert r = x"00" severity failure;
+
+    v <= "00100100";
+    wait for 1 ns;
+    assert r = x"02" severity failure;
+
+    v <= "11100111";
+    wait for 1 ns;
+    assert r = x"06" severity failure;
+
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/func01/testsuite.sh b/testsuite/synth/func01/testsuite.sh
index b08487cc4..c87986336 100755
--- a/testsuite/synth/func01/testsuite.sh
+++ b/testsuite/synth/func01/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in func01 func02 func03 func04 func05 func06; do
+for t in func01 func02 func03 func04 func05 func06 func07; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean