16 files changed, 503 insertions, 0 deletions

diff --git a/testsuite/gna/issue2395/test.vhdl b/testsuite/gna/issue2395/test.vhdl
new file mode 100644
index 000000000..7b467938e
--- /dev/null
+++ b/testsuite/gna/issue2395/test.vhdl
@@ -0,0 +1,64 @@
+library ieee ;
+    use ieee.std_logic_1164.all ;
+
+package axi4s is
+
+    type axis_t is record
+        data    :   std_ulogic_vector ;
+        dest    :   std_ulogic_vector ;
+        id      :   std_ulogic_vector ;
+        strb    :   std_ulogic_vector ;
+        keep    :   std_ulogic_vector ;
+        user    :   std_ulogic_vector ;
+        last    :   std_ulogic ;
+        valid   :   std_ulogic ;
+        ready   :   std_ulogic ;
+    end record ;
+
+    type axis_array_t is array(natural range <>) of axis_t ;
+
+    package make is
+      generic (
+        DATA_BYTES  :   positive    := 4 ;
+        DEST_WIDTH  :   natural     := 0 ;
+        ID_WIDTH    :   natural     := 0 ;
+        USER_WIDTH  :   natural     := 0
+      ) ;
+
+        subtype DATA_RANGE is natural range DATA_BYTES*8-1 downto 0 ;
+        subtype DEST_RANGE is natural range DEST_WIDTH-1 downto 0 ;
+        subtype ID_RANGE   is natural range ID_WIDTH-1 downto 0 ;
+        subtype KEEP_RANGE is natural range DATA_BYTES-1 downto 0 ;
+        subtype USER_RANGE is natural range USER_WIDTH-1 downto 0 ;
+
+        subtype axis_t is axi4s.axis_t(
+            data(DATA_RANGE),
+            dest(DEST_RANGE),
+            id(ID_RANGE),
+            keep(KEEP_RANGE),
+            strb(KEEP_RANGE),
+            user(USER_RANGE)
+        ) ;
+
+    end package ;
+
+end package ;
+
+package axis32 is new work.axi4s.make ;
+
+entity test is
+  port (
+    clock   :   in  bit ;
+    reset   :   in  bit ;
+    rx      :   inout   work.axis32.axis_t ;
+    tx      :   inout   work.axi4s.axis_t(data(31 downto 0), dest(-1 downto 0), id(-1 downto 0), keep(3 downto 0), strb(-1 downto 0), user(-1 downto 0))
+  ) ;
+end entity ;
+
+architecture arch of test is
+
+begin
+
+    -- do nothing for now
+
+end architecture ;
diff --git a/testsuite/gna/issue2395/testsuite.sh b/testsuite/gna/issue2395/testsuite.sh
new file mode 100755
index 000000000..1d84c0f57
--- /dev/null
+++ b/testsuite/gna/issue2395/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze test.vhdl
+elab_simulate test
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/gna/issue2407/shift_register.vhdl b/testsuite/gna/issue2407/shift_register.vhdl
new file mode 100644
index 000000000..e96fc7cea
--- /dev/null
+++ b/testsuite/gna/issue2407/shift_register.vhdl
@@ -0,0 +1,34 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+entity shift_register is
+  generic (
+    -- number of stages
+    NUM_STAGES: natural := 11;
+    -- number of bits
+    BITS: natural := 4
+  );
+  port (
+    clk, rst: in std_logic;
+    x: in std_logic_vector (BITS - 1 downto 0);
+    y: out std_logic_vector (BITS - 1 downto 0)
+  );
+end entity;
+architecture rtl of shift_register
+is
+  type signed_array is array (natural range <>) of signed;
+  signal shift_reg: signed_array (1 to NUM_STAGES - 1)(BITS - 1 downto 0);
+begin
+  process (clk, rst)
+  begin
+    if rst
+    then
+      shift_reg <= (others => (others => '0'));
+    elsif rising_edge (clk)
+    then
+      shift_reg <= signed (x) & shift_reg (1 to NUM_STAGES - 2);
+    end if;
+  end process;
+  y <= std_logic_vector (shift_reg (NUM_STAGES - 1));
+end architecture;
+
diff --git a/testsuite/gna/issue2407/shift_register_tb.vhdl b/testsuite/gna/issue2407/shift_register_tb.vhdl
new file mode 100644
index 000000000..9c1d9c875
--- /dev/null
+++ b/testsuite/gna/issue2407/shift_register_tb.vhdl
@@ -0,0 +1,47 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.env.finish;
+entity shift_register_tb is
+end shift_register_tb;
+architecture sim of shift_register_tb
+is
+  constant clk_hz: integer := 100e6;
+  constant clk_period: time := 1 sec / clk_hz;
+  -- number of stages
+  constant NUM_STAGES: natural := 5;
+  -- number of bits
+  constant BITS: natural := 4;
+  signal clk: std_logic := '1';
+  signal rst: std_logic := '1';
+  signal x: std_logic_vector (BITS - 1 downto 0) := (others => '0');
+  signal y: std_logic_vector (BITS - 1 downto 0);
+begin
+  clk <= not clk after clk_period / 2;
+  DUT: entity work.shift_register (rtl)
+    generic map (NUM_STAGES => NUM_STAGES, BITS => BITS)
+    port map (clk => clk, rst => rst, x => x, y => y);
+  SEQUENCER_PROC: process
+  begin
+    wait for clk_period * 2;
+    rst <= '0';
+    wait for clk_period;
+    for i in - 2** (BITS - 1) to 2** (BITS - 1) - 1 loop
+      x <= std_logic_vector (to_signed (i, BITS));
+      wait for clk_period;
+    end loop;
+    wait;
+  end process;
+  CHECK_PROC: process
+  begin
+    wait on rst;
+    wait for (NUM_STAGES + 1) * clk_period;
+    for i in - 2** (BITS - 1) to 2** (BITS - 1) - 1 loop
+      assert to_integer (signed (y)) = i report "y: " & to_string (to_integer (signed (y))) & " is not equal to " & to_string (i) severity failure;
+      wait for clk_period;
+    end loop;
+    wait for clk_period;
+    finish;
+  end process;
+end architecture;
+
diff --git a/testsuite/gna/issue2407/testsuite.sh b/testsuite/gna/issue2407/testsuite.sh
new file mode 100755
index 000000000..fe0f65add
--- /dev/null
+++ b/testsuite/gna/issue2407/testsuite.sh
@@ -0,0 +1,12 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze shift_register.vhdl
+analyze shift_register_tb.vhdl
+elab_simulate shift_register_tb
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/gna/issue2410/test.vhdl b/testsuite/gna/issue2410/test.vhdl
new file mode 100644
index 000000000..280452526
--- /dev/null
+++ b/testsuite/gna/issue2410/test.vhdl
@@ -0,0 +1,28 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test is
+end entity test;
+architecture beh of test is
+   type    t_slv_array is array (natural range <>) of std_logic_vector;
+   subtype t_word_array is t_slv_array(open)(15 downto 0);
+
+  procedure test_proc(
+    variable sig : out t_word_array)
+  is
+    variable v_sig : t_word_array(0 to sig'length);
+  begin
+    v_sig := (others => x"AAAA");
+    sig := v_sig(1 to sig'length);
+  end procedure;
+begin
+  
+  process
+    variable v_sig : t_word_array(0 to 0);
+  begin
+    test_proc(v_sig);
+    wait;
+  end process;
+
+end architecture beh;
diff --git a/testsuite/gna/issue2410/testsuite.sh b/testsuite/gna/issue2410/testsuite.sh
new file mode 100755
index 000000000..1d84c0f57
--- /dev/null
+++ b/testsuite/gna/issue2410/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+export GHDL_STD_FLAGS=--std=08
+analyze test.vhdl
+elab_simulate test
+
+clean
+
+echo "Test successful"
diff --git a/testsuite/synth/issue1079/tb_test2.vhdl b/testsuite/synth/issue1079/tb_test2.vhdl
new file mode 100644
index 000000000..27f6037b0
--- /dev/null
+++ b/testsuite/synth/issue1079/tb_test2.vhdl
@@ -0,0 +1,58 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tb_test2 is
+end;
+
+architecture behav of tb_test2 is
+  signal clk     : std_logic;
+  signal rd_en   : std_logic;
+  signal rd_addr : std_logic_vector(7 downto 0);
+  signal rd_data : std_logic_vector(63 downto 0);
+  signal wr_en   : std_logic;
+  signal wr_sel  : std_logic_vector(7 downto 0);
+  signal wr_addr : std_logic_vector(7 downto 0);
+  signal wr_data : std_logic_vector(63 downto 0);
+begin
+  inst_test2: entity work.test2
+    port map (
+      clk     => clk,
+      rd_en   => rd_en,
+      rd_addr => rd_addr,
+      rd_data => rd_data,
+      wr_en   => wr_en,
+      wr_sel  => wr_sel,
+      wr_addr => wr_addr,
+      wr_data => wr_data);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 5 ns;
+      clk <= '1';
+      wait for 5 ns;
+    end pulse;
+  begin
+    rd_en <= '0';
+    wr_en <= '0';
+    wr_sel <= x"ff";
+    pulse;
+
+    wr_en <= '1';
+    wr_addr <= x"01";
+    wr_data <= x"01_12_34_56_78_9a_bc_de";
+    pulse;
+
+    wr_en <= '1';
+    wr_addr <= x"02";
+    wr_data <= x"02_12_34_56_78_9a_bc_de";
+
+    rd_en <= '1';
+    rd_addr <= x"01";
+    pulse;
+
+    assert rd_data = x"01_12_34_56_78_9a_bc_de";
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1079/tb_test2n.vhdl b/testsuite/synth/issue1079/tb_test2n.vhdl
new file mode 100644
index 000000000..90f975f1c
--- /dev/null
+++ b/testsuite/synth/issue1079/tb_test2n.vhdl
@@ -0,0 +1,53 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity tb_test2n is
+end;
+
+architecture behav of tb_test2n is
+  signal clk     : std_logic;
+  signal rd_addr : std_logic_vector(7 downto 0);
+  signal rd_data : std_logic_vector(63 downto 0);
+  signal en   : std_logic;
+  signal wr_sel  : std_logic_vector(7 downto 0);
+  signal wr_addr : std_logic_vector(7 downto 0);
+  signal wr_data : std_logic_vector(63 downto 0);
+begin
+  inst_test2n: entity work.test2n
+    port map (
+      clk     => clk,
+      en      => en,
+      rd_addr => rd_addr,
+      rd_data => rd_data,
+      wr_sel  => wr_sel,
+      wr_addr => wr_addr,
+      wr_data => wr_data);
+
+  process
+    procedure pulse is
+    begin
+      clk <= '0';
+      wait for 5 ns;
+      clk <= '1';
+      wait for 5 ns;
+    end pulse;
+  begin
+    en <= '0';
+    wr_sel <= x"ff";
+    pulse;
+
+    en <= '1';
+    wr_addr <= x"01";
+    wr_data <= x"01_12_34_56_78_9a_bc_de";
+    pulse;
+
+    wr_addr <= x"02";
+    wr_data <= x"02_12_34_56_78_9a_bc_de";
+
+    rd_addr <= x"01";
+    pulse;
+
+    assert rd_data = x"01_12_34_56_78_9a_bc_de";
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/issue1079/test2.vhdl b/testsuite/synth/issue1079/test2.vhdl
new file mode 100644
index 000000000..a3234e0d9
--- /dev/null
+++ b/testsuite/synth/issue1079/test2.vhdl
@@ -0,0 +1,41 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test2 is
+    port(
+	clk     : in  std_logic;
+
+	rd_en   : in  std_logic;
+	rd_addr : in  std_logic_vector(7 downto 0);
+	rd_data : out std_logic_vector(63 downto 0);
+
+	wr_en   : in  std_logic;
+	wr_sel  : in  std_logic_vector(7 downto 0);
+	wr_addr : in  std_logic_vector(7 downto 0);
+	wr_data : in  std_logic_vector(63 downto 0)
+	);
+end test2;
+
+architecture rtl of test2 is
+    constant SIZE : integer := 2**8;
+    type ram_type is array (0 to SIZE - 1) of std_logic_vector(63 downto 0);
+    signal ram : ram_type;
+    signal rd_data0 : std_logic_vector(63 downto 0);
+begin
+    process(clk)
+	variable widx : integer range 0 to SIZE - 1;
+    begin
+	if rising_edge(clk) then
+	    if wr_en = '1' then
+		widx := to_integer(unsigned(wr_addr));
+                ram(widx) <= wr_data;
+	    end if;
+	    if rd_en = '1' then
+		rd_data0 <= ram(to_integer(unsigned(rd_addr)));
+	    end if;
+	end if;
+    end process;
+
+    rd_data <= rd_data0;
+end;
diff --git a/testsuite/synth/issue1079/test2n.vhdl b/testsuite/synth/issue1079/test2n.vhdl
new file mode 100644
index 000000000..f1890825d
--- /dev/null
+++ b/testsuite/synth/issue1079/test2n.vhdl
@@ -0,0 +1,38 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test2n is
+    port(
+	clk     : in  std_logic;
+	en   : in  std_logic;
+
+	rd_addr : in  std_logic_vector(7 downto 0);
+	rd_data : out std_logic_vector(63 downto 0);
+
+	wr_sel  : in  std_logic_vector(7 downto 0);
+	wr_addr : in  std_logic_vector(7 downto 0);
+	wr_data : in  std_logic_vector(63 downto 0)
+	);
+end test2n;
+
+architecture rtl of test2n is
+    constant SIZE : integer := 2**8;
+    type ram_type is array (0 to SIZE - 1) of std_logic_vector(63 downto 0);
+    signal ram : ram_type;
+    signal rd_data0 : std_logic_vector(63 downto 0);
+begin
+    process(clk)
+	variable widx : integer range 0 to SIZE - 1;
+    begin
+	if rising_edge(clk) then
+	    if en /= '0' then
+		widx := to_integer(unsigned(wr_addr));
+                ram(widx) <= wr_data;
+		rd_data0 <= ram(to_integer(unsigned(rd_addr)));
+	    end if;
+	end if;
+    end process;
+
+    rd_data <= rd_data0;
+end;
diff --git a/testsuite/synth/issue1079/testsuite.sh b/testsuite/synth/issue1079/testsuite.sh
index 875f6aa57..4c17ce169 100755
--- a/testsuite/synth/issue1079/testsuite.sh
+++ b/testsuite/synth/issue1079/testsuite.sh
@@ -5,4 +5,7 @@
 synth --out=raw test.vhdl -e > syn_test.raw
 grep -q mem_rd_sync syn_test.raw
 
+synth_tb test2
+synth_tb test2n
+
 echo "Test successful"
diff --git a/testsuite/synth/issue2408/bug.vhdl b/testsuite/synth/issue2408/bug.vhdl
new file mode 100644
index 000000000..179b30298
--- /dev/null
+++ b/testsuite/synth/issue2408/bug.vhdl
@@ -0,0 +1,39 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_arith.all;
+
+entity bug is
+	generic(
+		LEN : positive := 32;
+        POS : natural := 10
+	);
+	port(
+		output  : out signed(LEN-1 downto 0)
+	);
+
+    function GET_NUM_FUNC(n : natural) return integer is
+	variable result	:integer;
+	begin
+		case n is
+			when 0 => result := 16#010020#;
+			when 1 => result := 16#020D30#;
+			when 2 => result := 16#00FC1#;
+			when 3 => result := 16#05010#;
+			when 4 => result := 16#02800#;
+			when 5 => result := 16#01400#;
+			when 6 => result := 16#002F#;
+			when 7 => result := 16#0508#;
+			when 8 => result := 16#0200#;
+			when 9 => result := 16#0100#;
+			when 10 => result := 16#0A0#;
+			when others => result := 16#0#;
+		end case;
+		return result;
+	end GET_NUM_FUNC;
+
+end bug;
+
+architecture behav of bug is
+begin
+	output <= conv_signed(GET_NUM_FUNC(POS), LEN);
+end architecture;
diff --git a/testsuite/synth/issue2408/testsuite.sh b/testsuite/synth/issue2408/testsuite.sh
new file mode 100755
index 000000000..7de7b802c
--- /dev/null
+++ b/testsuite/synth/issue2408/testsuite.sh
@@ -0,0 +1,8 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=-fsynopsys
+synth_only bug
+
+echo "Test successful"
diff --git a/testsuite/synth/synth183/test.vhdl b/testsuite/synth/synth183/test.vhdl
new file mode 100644
index 000000000..84fc93639
--- /dev/null
+++ b/testsuite/synth/synth183/test.vhdl
@@ -0,0 +1,45 @@
+library ieee;

+    use ieee.std_logic_1164.all;

+

+entity test is

+    generic (

+        BAUD_MULT   : positive := 16

+    );

+    port (

+        clk, rst    : in std_logic;

+

+        brk         : out std_logic;

+        rx          : in std_logic

+    );

+end test;

+

+architecture behavioral of test is

+

+    signal rx_buf   : std_logic := '1';

+    signal break    : std_logic := '0';

+

+begin

+

+    BREAK_DETECTOR: process (clk, rst) is

+        constant BREAK_CNT : positive := BAUD_MULT * 11;

+        variable count : natural range 0 to BREAK_CNT + 1 := 0;

+    begin

+        if (rising_edge(clk)) then

+            rx_buf      <= rx;

+            -- Add to counter if '0', but halt count when break detected

+            count := (count + 1) when not(rx_buf or break);

+            -- Reset counter if '1'

+            count := 0 when rx_buf; 

+

+            break <= '0' when (count < BREAK_CNT) else '1';

+

+            if (rst = '1') then

+                count := 0;

+                break <= '0';

+            end if;

+        end if;

+    end process;

+

+    brk <= break;

+

+end behavioral;
\ No newline at end of file
diff --git a/testsuite/synth/synth183/testsuite.sh b/testsuite/synth/synth183/testsuite.sh
new file mode 100755
index 000000000..eb1ca0714
--- /dev/null
+++ b/testsuite/synth/synth183/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+
+synth_analyze test
+
+clean
+
+echo "Test successful"