3 files changed, 45 insertions, 0 deletions
diff --git a/testsuite/synth/sns01/add03.vhdl b/testsuite/synth/sns01/add03.vhdl
new file mode 100644
index 000000000..16546bd0d
--- /dev/null
+++ b/testsuite/synth/sns01/add03.vhdl
@@ -0,0 +1,19 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+entity add03 is
+  port (
+    a, b : std_logic_vector(8 DOWNTO 0);
+    borrow : std_logic;
+    res : out std_logic_vector(8 DOWNTO 0));
+end add03;
+
+LIBRARY ieee;
+USE ieee.std_logic_arith.all;
+
+architecture behav of add03 is
+  signal t : signed(8 DOWNTO 0);
+begin
+  t <= signed(a) - signed(b) - borrow;
+  res <= std_logic_vector(t);
+end behav;
diff --git a/testsuite/synth/sns01/tb_add03.vhdl b/testsuite/synth/sns01/tb_add03.vhdl
new file mode 100644
index 000000000..7bc68ea8a
--- /dev/null
+++ b/testsuite/synth/sns01/tb_add03.vhdl
@@ -0,0 +1,24 @@
+entity tb_add03 is
+end tb_add03;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_add03 is
+  signal a, b : std_logic_vector(8 DOWNTO 0);
+  signal borrow : std_logic;
+  signal res : std_logic_vector(8 DOWNTO 0);
+begin
+  dut: entity work.add03
+    port map (a, b, borrow, res);
+
+  process
+  begin
+    a <= b"00000_0100";
+    b <= b"00000_0001";
+    borrow <= '0';
+    wait for 1 ns;
+    assert res = b"00000_0011" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/sns01/testsuite.sh b/testsuite/synth/sns01/testsuite.sh
index d9cb4503a..a93cc4530 100755
--- a/testsuite/synth/sns01/testsuite.sh
+++ b/testsuite/synth/sns01/testsuite.sh
@@ -15,4 +15,6 @@ done
 synth_analyze sns02
 clean
 
+synth_tb add03
+
 echo "Test successful"