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* vhdl: recognize PSL units reserved words.Tristan Gingold2019-08-169-737/+774
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* testsuite/python: fix test name (to follow the testsuite.sh convention)Tristan Gingold2019-08-163-0/+0
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* synth: handle array attributes; handle integer subtypes in generics.Tristan Gingold2019-08-162-2/+91
| | | | Fix tgingold/ghdlsynth-beta#32
* Makefile.in: install synth include files as part of libghdl.Tristan Gingold2019-08-151-1/+6
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* configure: complete --helpTristan Gingold2019-08-151-0/+2
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* testsuite/synth: fix assert1 assertion.Tristan Gingold2019-08-151-1/+1
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* add synthesis support for logic operators on numeric types (#893)Pepijn de Vos2019-08-155-7/+152
| | | | | | | | * add logic operators on unsigned * handle signed too * handle unary not
* synth: fix handling of assume/assert.Tristan Gingold2019-08-141-6/+65
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* ghdlsynth: add command to get libghdl paths.Tristan Gingold2019-08-144-22/+97
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* ghdldrv: move command_str_disp from ghdlvpi to ghdlmainTristan Gingold2019-08-143-38/+38
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* testenv: also applies GHDL_FLAGS for synth.Tristan Gingold2019-08-141-1/+1
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* ghdlsynth: declare init_for_ghdl_synth.Tristan Gingold2019-08-141-1/+4
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* update NEWS.md. Fix #891Tristan Gingold2019-08-141-1/+8
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* synth: add test for previous commit.Tristan Gingold2019-08-143-2/+29
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* vhdl: handle PSL keywords as vhdl08 reserved words; switch to PSL scanner mode.Tristan Gingold2019-08-142-0/+12
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* vhdl: add PSL keywords to vhdl08 reserved words.Tristan Gingold2019-08-1410-242/+257
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* testsuite/gna: use common testsuite.shTristan Gingold2019-08-141-14/+5
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* testsuite/gna/README: document naming convention.Tristan Gingold2019-08-141-2/+11
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* testsuite/gna: make testsuite.py neutral.Tristan Gingold2019-08-141-4/+1
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* testsuite/gna: rename perf02 to not run it normally.Tristan Gingold2019-08-1436-0/+0
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* testsuite/synth: make testsuite.sh more neutral.Tristan Gingold2019-08-141-2/+2
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* testsuite/testenv.sh: define PYTHONTristan Gingold2019-08-141-0/+2
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* testsuite/python: add testsuite.shTristan Gingold2019-08-141-0/+53
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* testsuite: add testsuite.sh in 001unitsTristan Gingold2019-08-141-0/+7
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* Fix build of upf packages for openieee.Tristan Gingold2019-08-141-5/+5
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* synth: also extract edge in PSL expressions.Tristan Gingold2019-08-135-19/+64
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* synth: extract edge for PSL clocks.Tristan Gingold2019-08-135-29/+120
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* vhdl-nodes_walk: handle iir_kind_psl_default_clock.Tristan Gingold2019-08-131-1/+2
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* libghdlsynth: make it almost empty, as libghdl will be used instead.Tristan Gingold2019-08-131-8/+0
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* Support for PSL assert and assume in synthesis (#892)Pepijn de Vos2019-08-132-5/+55
| | | | | | | | * initial support for PSL assert and assume * add support for true, false, and, or in psl synth * update testsuite with new psl things
* libghdl: also add synthesis part. For #884Tristan Gingold2019-08-137-55/+61
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* synth: build_header was replaced by a Makefile target.Tristan Gingold2019-08-131-8/+0
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* libghdl: preliminary work to also support synth.Tristan Gingold2019-08-133-4/+10
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* openieee: add dummy UPF package (#889)1138-4EB2019-08-113-1/+47
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* vhdl: improve reprint of inertial association.Tristan Gingold2019-08-116-181/+206
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* Add testcase for #885Tristan Gingold2019-08-112-0/+44
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* vhdl-sem: fix minor thinko for sem_insert_anonymous_signal.Tristan Gingold2019-08-111-1/+24
| | | | Fix #885
* Add testcase for #886Tristan Gingold2019-08-105-0/+141
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* vhdl: avoid crash on incorrect unit name.Tristan Gingold2019-08-102-6/+36
| | | | Fix #886
* vhdl: handle subtype indication (with range) in discrete_range.Tristan Gingold2019-08-107-63/+105
| | | | For #877
* synth: add comments.Tristan Gingold2019-08-091-1/+9
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* vhdl: remove unused Get/Set_Choice_Order.Tristan Gingold2019-08-097-580/+515
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* synth: add testcase from #872Tristan Gingold2019-08-082-0/+51
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* synth: add testcase for aggregate target.Tristan Gingold2019-08-083-0/+56
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* synth: fix crash when assignment target is an aggregate.Tristan Gingold2019-08-081-5/+7
| | | | For tgingold/ghdlsynth-beta#26
* vhdl: remove -Whides warnings for processes without a label.Tristan Gingold2019-08-081-0/+9
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* Add reproducer for tgingold/ghdlsynth-beta#26Tristan Gingold2019-08-082-0/+29
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* synth: handle 1 bit integer in disp_vhdl, fix range in synth-expr.Tristan Gingold2019-08-082-4/+13
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* vhdl: remove severity from cover, report and severity from assume.Tristan Gingold2019-08-0811-142/+160
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* pnodes.py: be strict about comments, refactoring.Tristan Gingold2019-08-071-42/+62
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