| Commit message (Collapse) | Author | Age | Files | Lines | ||
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| * | synth: handle resize. | Tristan Gingold | 2019-07-24 | 1 | -0/+15 | |
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| * | synth: handle record type declarations. | Tristan Gingold | 2019-07-24 | 1 | -1/+11 | |
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| * | vhdl: recognize resize function. | Tristan Gingold | 2019-07-24 | 4 | -3/+43 | |
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| * | synth: add testcase for previous commit. | Tristan Gingold | 2019-07-23 | 3 | -0/+81 | |
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| * | synth: fix slice/indexed assignment that partially override previous assign. | Tristan Gingold | 2019-07-23 | 1 | -5/+8 | |
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| * | synth: add more operators. | Tristan Gingold | 2019-07-23 | 1 | -1/+34 | |
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| * | synth: fix to_unsigned. | Tristan Gingold | 2019-07-23 | 1 | -2/+2 | |
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| * | synth: use original entity to display netlist. | Tristan Gingold | 2019-07-23 | 7 | -22/+314 | |
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| * | vhdl-prints: improve output for ports/generics. | Tristan Gingold | 2019-07-22 | 1 | -5/+27 | |
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| * | synth: remove bounds (unused) for ports. | Tristan Gingold | 2019-07-22 | 4 | -13/+4 | |
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| * | ghdlsynth: preliminary work for wrapped generation. | Tristan Gingold | 2019-07-22 | 1 | -1/+8 | |
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| * | synth: minor refactoring in netlists.disp_vhdl | Tristan Gingold | 2019-07-22 | 2 | -47/+54 | |
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| * | synth: minor rework. | Tristan Gingold | 2019-07-22 | 3 | -10/+37 | |
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| * | synth: rework names. | Tristan Gingold | 2019-07-22 | 6 | -24/+25 | |
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| * | vhdl: add testcase. | Tristan Gingold | 2019-07-22 | 2 | -0/+93 | |
| | | | | | Close #875 | |||||
| * | add port width utility function for yosys (#876) | Pepijn de Vos | 2019-07-21 | 4 | -0/+18 | |
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| * | synth: improve output (id_extract). | Tristan Gingold | 2019-07-20 | 1 | -6/+12 | |
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| * | synth: improve output (for id_insert). | Tristan Gingold | 2019-07-20 | 1 | -11/+18 | |
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| * | synth: fix test name. | Tristan Gingold | 2019-07-20 | 3 | -0/+0 | |
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| * | synth: add testcase for concurrent selected signal assignment. | Tristan Gingold | 2019-07-20 | 3 | -0/+75 | |
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| * | synth: add support for concurrent selected signal assignment. | Tristan Gingold | 2019-07-20 | 1 | -2/+138 | |
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| * | synth: add a test for for-generate statement. | Tristan Gingold | 2019-07-20 | 3 | -0/+49 | |
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| * | synth: support index of a constant. | Tristan Gingold | 2019-07-20 | 1 | -0/+4 | |
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| * | synth: initial support for for-generate statement. | Tristan Gingold | 2019-07-20 | 3 | -34/+97 | |
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| * | synth: add a test for previous commit. | Tristan Gingold | 2019-07-20 | 5 | -0/+111 | |
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| * | synth: add and merge phi within a function. | Tristan Gingold | 2019-07-20 | 1 | -0/+5 | |
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| * | synth: add a test for previous commit (aggr). | Tristan Gingold | 2019-07-20 | 5 | -0/+101 | |
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| * | synth: fix aggregate vectorize direction. | Tristan Gingold | 2019-07-20 | 2 | -5/+6 | |
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| * | synth: add concatn gate | Tristan Gingold | 2019-07-19 | 9 | -32/+126 | |
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| * | synth: add testcase from issue8 | Tristan Gingold | 2019-07-19 | 8 | -0/+156 | |
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| * | synth: finalize concurrent assignments (WIP). | Tristan Gingold | 2019-07-19 | 6 | -33/+342 | |
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| * | synth: add const_z gate. | Tristan Gingold | 2019-07-19 | 4 | -3/+33 | |
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| * | synth: add a test for concatenation. | Tristan Gingold | 2019-07-19 | 3 | -0/+62 | |
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| * | errorout: handle %v for values. | Tristan Gingold | 2019-07-19 | 2 | -1/+36 | |
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| * | synth: make more types private. | Tristan Gingold | 2019-07-17 | 2 | -35/+48 | |
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| * | synth: make type Wire_Id_Record private. | Tristan Gingold | 2019-07-17 | 7 | -44/+74 | |
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| * | synth: renaming of Assign to Seq_Assign. | Tristan Gingold | 2019-07-17 | 6 | -79/+82 | |
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| * | synth: add comments. | Tristan Gingold | 2019-07-17 | 2 | -0/+2 | |
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| * | Add a testcase about distinct alternate labels. | Tristan Gingold | 2019-07-16 | 3 | -0/+145 | |
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| * | vhdl: add a comment. | Tristan Gingold | 2019-07-16 | 1 | -0/+3 | |
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| * | synth: add > and >= operators (#870) | Pepijn de Vos | 2019-07-16 | 6 | -25/+118 | |
| | | | | | | | * synth: add > and >= operators * synth: update ghdlsynth_gates.h | |||||
| * | Add testcase for #869 | Tristan Gingold | 2019-07-15 | 2 | -0/+30 | |
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| * | vhdl: avoid a crash on no matching operator error. | Tristan Gingold | 2019-07-15 | 1 | -1/+7 | |
| | | | | | Fix #869 | |||||
| * | vhdl-sem_names: avoid a crash on parenthesis of | Tristan Gingold | 2019-07-15 | 1 | -2/+2 | |
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| * | find_top_entity: avoid crash on missing entity, handle | Tristan Gingold | 2019-07-15 | 2 | -13/+27 | |
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| * | synth: handle instantiation within generate statement. | Tristan Gingold | 2019-07-15 | 1 | -0/+2 | |
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| * | ghdlsynth: quit early in case of error. | Tristan Gingold | 2019-07-15 | 1 | -1/+10 | |
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| * | synth: handle choices by range in aggregates. | Tristan Gingold | 2019-07-15 | 3 | -12/+33 | |
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| * | synth: handle anonymous subtypes in array subtypes. | Tristan Gingold | 2019-07-15 | 1 | -4/+10 | |
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| * | synth: add comments. | Tristan Gingold | 2019-07-15 | 1 | -6/+10 | |
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index : iCE40/ghdl | |
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