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* | vhdl-annotations: avoid a crash with subtype attribute in array.Tristan Gingold2022-06-093-5/+16
| | | | | | | | Fix #2084
* | testsuite/synth: add a test for #2083Tristan Gingold2022-06-082-0/+39
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* | synth-vhdl_expr.adb: use base type for indexed names. Fix #2083Tristan Gingold2022-06-081-1/+2
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* | synth-vhdl_expr: add an hook for signal attributesTristan Gingold2022-06-082-0/+11
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* | Makefile.in: tentatively use shared-libgcc for ghdl_mcodeTristan Gingold2022-06-081-1/+1
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* | synth-vhdl_eval: handle more operationsTristan Gingold2022-06-071-8/+17
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* | vhdl-sem: adjust condition to set suspend_state on proceduresTristan Gingold2022-06-074-269/+291
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* | elab-vhdl_context: also handle generic subprogramsTristan Gingold2022-06-071-2/+6
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* | options.adb: add commandsTristan Gingold2022-06-071-2/+2
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* | pyGHDL: regenerateTristan Gingold2022-06-071-10/+11
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* | testsuite/synth: add a test for #2081Tristan Gingold2022-06-072-0/+25
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* | errorout: add nowrite warning. Fix #2081Tristan Gingold2022-06-075-8/+16
| | | | | | | | During synthesis, emit a specific warning if a net is not assigned
* | testsuite/gna: add one test for #2076Tristan Gingold2022-06-062-0/+5
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* | vhdl-parse.adb: fix uninitialized variable, for #2076Tristan Gingold2022-06-061-0/+1
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* | testsuite/gna: add tests for #2076Tristan Gingold2022-06-063-0/+34
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* | vhdl-sem_names: avoid a crash on incorrect selected name. For #2076Tristan Gingold2022-06-061-1/+2
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* | vhdl-parse: avoid a crash with return identifier. Fox #2076Tristan Gingold2022-06-061-1/+7
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* | synth-vhdl_stmts: fix handling of instantiated subprogramsTristan Gingold2022-06-061-1/+3
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* | synth-vhdl_eval: handle more operationsTristan Gingold2022-06-061-1/+16
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* | synth-vhdl_stmts: handle alias in assignment expressionTristan Gingold2022-06-063-2/+24
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* | vhdl-ieee-math_real: recognize more operationsTristan Gingold2022-06-063-230/+285
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* | synth-vhdl_eval: recognize and handle to_stdulogicvectorTristan Gingold2022-06-064-224/+241
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* | synth-vhdl_eval: handle more operationsTristan Gingold2022-06-052-37/+112
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* | vhdl: recognize more predefined ieee functions and operatorsTristan Gingold2022-06-055-465/+593
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* | synth-vhdl_eval: handle more operations (sgn/uns reduce)Tristan Gingold2022-06-051-6/+16
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* | synth-vhdl-eval: handle more operationsTristan Gingold2022-06-054-31/+272
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* | vhdl-ieee-numeric: recognize vector/scalar operationsTristan Gingold2022-06-053-296/+368
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* | testsuite/synth: add a test for #2074Tristan Gingold2022-06-052-0/+25
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* | synth-vhdl_oper: handle more bit_vector operations. Fix #2074Tristan Gingold2022-06-051-8/+13
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* | elab-debugger: add where commandTristan Gingold2022-06-051-28/+49
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* | synth-vhdl_eval: handle rotations and shift for numeric_stdTristan Gingold2022-06-051-4/+40
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* | synth-vhdl_eval: handle to_x01, to_ux01, to_x01z and is_xTristan Gingold2022-06-052-19/+56
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* | vhdl-ieee-numeric: recognize is_x, to_x01, to_ux01 and to_x01zTristan Gingold2022-06-053-234/+284
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* | synth-vhdl_eval: handle more operationsTristan Gingold2022-06-053-2/+41
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* | synth-ieee-numeric_std: fix handling of X for negationTristan Gingold2022-06-051-18/+20
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* | synth-vhdl_eval: handle find_leftmost and find_rightmostTristan Gingold2022-06-053-0/+55
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* | testsuite/synth: add a test for #2073Tristan Gingold2022-06-054-0/+185
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* | synth-vhdl_expr: adjust max computation for memidx. Fix #2073Tristan Gingold2022-06-052-3/+3
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* | pyGHDL/lsp: reformatTristan Gingold2022-06-041-3/+1
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* | testsuite/synth: add a test for #2072Tristan Gingold2022-06-043-0/+80
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* | synth-vhdl_decls: fix subtype conversion for variable default value.Tristan Gingold2022-06-041-1/+1
| | | | | | | | Fix #2072
* | synth-vhdl_eval: handle minmaxTristan Gingold2022-06-043-178/+295
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* | pyGHDL/lsp: enable warning for unassociated portsTristan Gingold2022-06-041-0/+1
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* | vhdl: add a warning for unassociated portsTristan Gingold2022-06-045-13/+31
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* | pyGHDL/lsp: handle goto-reference on records elementsTristan Gingold2022-06-041-1/+3
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* | testsuite/gna: add a test for previous commitTristan Gingold2022-06-042-0/+12
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* | vhdl-sem_types: avoid a crash on empty records if forced analysisTristan Gingold2022-06-041-1/+9
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* | synth-vhdl_expr: do not abort on array subtype conversionTristan Gingold2022-06-042-1/+6
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* | vhdl-sem_scopes: handle state_suspendTristan Gingold2022-06-041-1/+2
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* | elab-vhdl_debug: add print commandTristan Gingold2022-06-044-2/+306
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