iCE40/ghdl - [no description]

	Commit message (Collapse)	Author	Age	Files	Lines
*	synth: propagate assignments out of subprograms. Fix #960	Tristan Gingold	2019-10-06	1	-0/+7
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*	synth: finalize declarations and free wires.	Tristan Gingold	2019-09-27	1	-0/+17
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*	synth: improve locations tracking.	Tristan Gingold	2019-09-18	1	-1/+2
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*	synth: fold addition on constant nets.	Tristan Gingold	2019-09-17	1	-0/+8
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*	synth: improve support of return statement.	Tristan Gingold	2019-09-11	1	-0/+1
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*	synth: handle partial assignments in case statements.	Tristan Gingold	2019-09-07	1	-5/+36
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*	synth: add support for record types.	Tristan Gingold	2019-08-29	1	-0/+5
\| \| \| \|	(WIP: need to fix regression of stmt01).
*	synth: rework partial assignments	Tristan Gingold	2019-08-27	1	-8/+38
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*	synth: add comments.	Tristan Gingold	2019-08-09	1	-1/+9
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*	synth: refactoring in inference/environment.	Tristan Gingold	2019-08-01	1	-0/+2
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*	synth: refactor inference, add comment, strengthen check.	Tristan Gingold	2019-08-01	1	-0/+2
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*	synth: finalize concurrent assignments (WIP).	Tristan Gingold	2019-07-19	1	-1/+26
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*	synth: make more types private.	Tristan Gingold	2019-07-17	1	-34/+47
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*	synth: make type Wire_Id_Record private.	Tristan Gingold	2019-07-17	1	-23/+37
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*	synth: renaming of Assign to Seq_Assign.	Tristan Gingold	2019-07-17	1	-14/+15
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*	synth: add comments.	Tristan Gingold	2019-07-17	1	-0/+1
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*	synth-environement: add comments.	Tristan Gingold	2019-07-08	1	-3/+2
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*	synth: add comments.	Tristan Gingold	2019-06-07	1	-3/+6
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*	Add netlist generation infrastructure.	Tristan Gingold	2017-01-31	1	-0/+153